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0.015UF100VDC1206

Vendor: AVX
D/C: 2004/PF

Description

Note 1: Gain error tested at VREF = +2.0V, +2.5V, and +3.0V (MAX5143/MAX5144) or VREF = +2.0V, +2.5V, +3.0V, and +5.0V (MAX5141/MAX5142). Note 2: ROUT tolerance is typically 20%. Note 3: Min/max range guaranteed by gain-error test. Operation outside min/max limits will result in degraded performance. Note 4: Reference input resistance is code dependent, minimum at 2155 hex in unipolar mode, 1155 hex in bipolar mode. Note 5: Slew-rate value is measured from 10% to 90%. Note 6: Guaranteed by design. Not production tested. Note 7: Guaranteed by power-supply rejection test and Timing Characteristics.

Applications

The SN74AVCB324245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated.

Features

Each I/O cell drives a unique pin. The OE control for each I/O pin is independent and may be driven via the GRP by one of the designated I/O pins (I/O-OE set). The I/O-OE set consists of 25% of the total I/O pins. Boundary Scan test is supported by dedicated registers at each I/O pin. In-system programming is accomplished through the standard Boundary Scan protocol.

Supplier

  • Part Name
  • Q'ty
  • Description
  • Vendor
  • Date Code
  • Date
  • Quotation
  • 0.00150V0805
  • 4000/REEL
  • skype:treesam_xie yahoo messager:treesamxie
  • TDK
  • 2017-10-19

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