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0.027UF250VDC18125

Vendor: N/A

Description

Following the address and acknowledge bit with logic 0 in the read/write bit, the first byte written is the command byte. If the command byte is reserved and therefore not valid, it will not be acknowledged. Only valid command bytes will be acknowledged.

Applications

‧SOP package 4 Pin type in miniature design (4.44.32.0mm / .173.169.083inch) ‧Low driver power requirements (TTL/CMOS Compatible) ‧High reliability ‧Arc-Free with no snubbing circuits ‧1500Vrms Input/Output isolation ‧Tape & Reel version available

Features

Inputs to VID D to A Converter Inputs to VID D to A Converter Connect a resistor to VOSNS- to program oscillator frequency and FB, OCSET, BBFB, and VDAC bias currents Remote Sense Input. Connect to ground at the Load. Programs the hiccup over-current threshold through an external resistor tied to VDAC and an internal current source. Regulated voltage programmed by the VID inputs. Current Sensing and Over Current Protection are referenced to this pin. Connect an external RC network to VOSNS- to program Dynamic VID slew rate. Buffered IIN signal. Connect an external RC network to FB to program converter output impedance Inverting input to the Error Amplifier. Converter output voltage is offset from the VDAC voltage through an external resistor connected to the converter output voltage at the load and an internal current source. Bias current is a function of ROSC. Also OVPsense. Output of the Error Amplifier Controls Converter Softstart, Power Good, and Over-Current Timing. Connect an external capacitor to LGND to program the timing. Compensation for the Current Share control loop. Connect a capacitor to ground to set the control loops bandwidth. Phase 2 is forced to match phase 1s current. No Connect. Local Ground and IC substrate connection External resistor to ground sets voltage at BIASOUT pin. Bias current is a function of ROSC. Power for internal circuitry and source for BIASOUT regulator No Connect. 150mA open-looped regulated voltage set by SETBIAS for GATE drive bias. Open Collector output that drives low during Softstart or any fault condition. Connect external pull-up. Non-inverting input to the Phase 2 Current Sense Amplifier. No Connect. Ground Selects VR10 VID, Float Selects OPTERON VID, VCC Selects ATHLON VID No Connect. Power for Phase 2 High-Side Gate Driver Phase 2 High-Side Gate Driver Output and input to GATEL2 non-overlap comparator. Return for Phase 2 Gate Drivers Phase 2 Low-Side Gate Driver Output and input to GATEH2 non-overlap comparator. Can be used to monitor the driver supply voltage or 5V supply voltage when converting from 5V. An under voltage condition initiates Soft Start. Power for Phase 1 and 2 Low-Side Gate Drivers. Phase 1 Low-Side Gate Driver Output and input to GATEH1 non-overlap comparator. Return for Phase 1 Gate Drivers Phase 1 High-Side Gate Driver Output and input to GATEL1 non-overlap comparator. Power for Phase 1 High-Side Gate Driver Not connected Inverting input to the Phase 1Current Sense Amplifier. Non-inverting input to the Current Sense Amplifier. Output that drives high during an Over-Voltage condition. Enable Input. A logic low applied to this pin puts the IC into Fault mode. No Connect. Inputs to VID D to A Converter Inputs to VID D to A Converter Inputs to VID D to A Converter Inputs to VID D to A Converter

Supplier

  • Part Name
  • Q'ty
  • Description
  • Vendor
  • Date Code
  • Date
  • Quotation
  • 0.00150V0805
  • 4000/REEL
  • skype:treesam_xie yahoo messager:treesamxie
  • TDK
  • 2017-10-18

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