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0.5W12V

Vendor: COS
Package Cooled: DO-35
D/C: 07+

Description

Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read

Applications

• Layer 2 priority encoding (802.3p) (up to 16 priority queues) • VLAN tagging (IEEE 802.3q) • Flow control (IEEE 802.3x) • Link aggregation (IEEE802.3ad) • Multiple power modes with programmable low power   operation • Low power design C 3.3 V/1.8 V, 0.18 µm CMOS • 5V tolerant PCI I/Os • 388-pin PBGA package

Features

drivers to drive either 3.3V or 2.5V output levels while the device logic and the output current drive is always pow- ered from 3.3V. The output drivers also provide individually programmable edge rates and open drain capability. A programmable pullup resistor is provided to tie off un- used inputs and a programmable bus-hold latch is available to hold tristate outputs in their last valid state until the bus is driven again by some device.

Supplier

  • Part Name
  • Q'ty
  • Description
  • Vendor
  • Date Code
  • Date
  • Quotation
  • 0.5W12V
  • 18700
  • COS
  • DO-35
  • 2017-10-19
  • 0.5W12V
  • 11250
  • COS
  • DO-35
  • 2017-10-19
  • 0.5W12V
  • 100
  • 原装库存,欢迎求购!
  • 2017-10-19
  • 0.5W12V
  • 9560
  • new &original0
  • COS
  • DO-35
  • 2017-10-19
  • 0.51R
  • 5000
  • 国巨
  • 05+
  • 2017-10-19
  • 0.5-3
  • 1,000
  • JST
  • JST RING TERMINAL
  • 2017-10-19
  • 0.5-4
  • 40
  • JST
  • JST RING TERMINAL
  • 2017-10-19
  • 0.5A
  • MICROFUSE
  • 全新原装现货
  • 5800
  • 0805+
  • 2017-10-19

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