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0.5W2.7V

Description

With 1mA load With 1mA load With 20pF maximum load capacitance mea- sured from 10% to 90% of output voltage Output at (VDD -0.3V) Output at 0.3V MCLK can be driven DC-coupled by a CMOS clock oscillator with rail-to-rail out- puts. Other oscillator configurations may require AC-coupling.

Applications

Notes:  1. SSSEL has internal pull-up and SSON has pull-down resistors.  2. In applications if a crystal is used for the input reference clock, refer to crystal manufacturers specifications for the required crystal load capacitor value.  3. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs. All outputs   loaded with 15 pF.  4. Measured between 0.2*VDD and 0.8*VDD Volts.  5. Triggering is done at 1.5V VDDC.

Features

• Interfaces directly to a single-scan panel monochrome   STN LCD • Interfaces to a single-scan panel color STN LCD with   minimal external glue logic • Panel width size is programmable from 32 to 1024   pixels in 16-pixel increments • Video frame buffer size programmable up to   128 KB • Bits per pixel of 1, 2, or 4 bits

Supplier

  • Part Name
  • Q'ty
  • Description
  • Vendor
  • Date Code
  • Date
  • Quotation
  • 0.5W2.7V
  • 100
  • 原装库存,欢迎求购!
  • 2017-10-19
  • 0.51R
  • 5000
  • 国巨
  • 05+
  • 2017-10-19
  • 0.5-3
  • 1,000
  • JST
  • JST RING TERMINAL
  • 2017-10-19
  • 0.5-4
  • 40
  • JST
  • JST RING TERMINAL
  • 2017-10-19
  • 0.5A
  • MICROFUSE
  • 全新原装现货
  • 5800
  • 0805+
  • 2017-10-19

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