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0.5W24V

Description

24421-009-DTS Rev ADQ# 2009 All technical information is believed to be accurate, but no responsibility is assumed for errors or omissions. Interpoint reserves the right to make changes in products or specifications without notice. HR300 Series is a trademark of Interpoint. Copyright © 1991 - 1999 Interpoint. All rights reserved.

Applications

NOTES:-  1. Derate linearly above 70oC free air temperature at a rate of 0.8 mA/C.  2. Derate linearly above 70oC free air temperature at a rate of 1.6 mA/C.  3. Derate linearly above 70oC free air temperature at a rate of 0.9 mW/C.  4. Derate linearly above 70oC free air temperature at a rate of 1.0 mW/C.  5. Each channel .  6. CURRENT TRANSFER RATIO is defined as the ratio of output collector current,IO , to the forward LED   input current, IF times 100%.  7. Device considered a two-terminal device: pins 1,2,3,and 4 shorted together and pins 5,6,7,and 8 shorted   together.  8. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.  9. Common mode transient immunity in Logic High level is the maximum tolerable (positive) dVcm/dt on   the leading edge of the common mode pulse VCM to assure that the output will remain in a Logic High   state (i.e. VO > 2.0V). Common mode transient immunity in Logic Low level is the maximum tolerable   (negative) dVcm/dt on the trailing edge of the common mode pulse signal, VCM to assure that the output   will remain in Logic Low state (i.e. VO< 0.8V).

Features

Depth expansion is possible using the cascade input (XI), cascade output (XO), and First Load (FL) pins. The XO pin is connected to the XI pin of the next device, and the XO pin of the last device should be connected to the XI pin of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC. When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a free-running read clock (RCLK) and a read enable pin (REN). In addition, the 0.5W24V/92 have an output enable pin (OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable.

Supplier

  • Part Name
  • Q'ty
  • Description
  • Vendor
  • Date Code
  • Date
  • Quotation
  • 0.5W24V
  • 100
  • 原装库存,欢迎求购!
  • 2017-10-19
  • 0.51R
  • 5000
  • 国巨
  • 05+
  • 2017-10-19
  • 0.5-3
  • 1,000
  • JST
  • JST RING TERMINAL
  • 2017-10-19
  • 0.5-4
  • 40
  • JST
  • JST RING TERMINAL
  • 2017-10-19
  • 0.5A
  • MICROFUSE
  • 全新原装现货
  • 5800
  • 0805+
  • 2017-10-19

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