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Hynix HYMP512S64MP8 series is designed for high speed and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 4- bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_1.8. High speed frequen- cies, programmable latencies and burst lengths allow variety of device operation in high performance memory system.


DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data bus. The outputs are enabled in the Program condition during the I/O Read to output the contents of a register to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle when the CPU is programming the 82C37A control registers. During DMA cycles, the most signifi- cant 8-bits of the address are output onto the data bus to be strobed into an external latch by AD- STB. In memory-to-memory operations, data from the memory enters the 82C37A on the data bus during the read-from-memory transfer, then during the write-to-memory transfer, the data bus out- puts write the data into the new memory location.


The TMS320C62x DSP offers cost-effective solutions to high-performance DSP programming challenges. The 0.5W33VB/03 has a performance of up to 2400 million instructions per second (MIPS) at 300 MHz, while the 0.5W33V has a performance of up to 2000 MIPS at 250 MHz, and the 0.5W33V has a performance of up to 1600 MIPS at 200 MHz. The C6202/02B/03/04 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. These processors have 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6202/02B/03/04 can produce two multiply-accumulates (MACs) per cycle. This gives a total of 600 million MACs per second (MMACS) for the C6202B/03 device, a total of 500 MMACS for the C6202 device, and a total of 400 MMACS for the C6204 device. The C6202/02B/03/04 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.


  • Part Name
  • Q'ty
  • Description
  • Vendor
  • Date Code
  • Date
  • Quotation
  • 0.5W33V
  • 100
  • 原装库存,欢迎求购!
  • 2017-10-18
  • 0.51R
  • 5000
  • 国巨
  • 05+
  • 2017-10-18
  • 0.5-3
  • 1,000
  • JST
  • 2017-10-18
  • 0.5-4
  • 40
  • JST
  • 2017-10-18
  • 0.5A
  • 全新原装现货
  • 5800
  • 0805+
  • 2017-10-18

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