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Vendor: ST
Package Cooled: 06+


When the BLANKING input is high, the output source drivers are disabled (OFF); the pnp active pull-down sink drivers are ON. The information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches.


Note 6: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For example, for a fOP of 1MHz, the period equals 1000ns. In this case if tCLH = is set to 410ns, then tCLL must be set to a minimum of 590ns.


Conditions DAC latches loaded with all 0s DAC latches loaded with all 1s Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s VREF = 5 V p-p, all 1s loaded, f = 1 kHz VREF = 5 V, sine wave generated from digital code @ 1 kHz AD5449, 65 k codes, VREF = 3.5 V


  • Part Name
  • Q'ty
  • Description
  • Vendor
  • Date Code
  • Date
  • Quotation
  • B22AJ823
  • 769
  • Special offer stock
  • ST
  • 2017-10-17
  • B22AJ823
  • 769
  • New Parts In stock
  • ST
  • STK
  • 2017-10-17
  • B22AJ823
  • 17
  • ST
  • 2017-10-17
  • B22AJ823
  • 138000
  • New and original
  • 2017-10-17
  • B220
  • 36000
  • liteon
  • liteon
  • 2017-10-17
  • B220
  • 23000
  • 2017-10-17
  • B220
  • 50000
  • 2017-10-17
  • B220
  • 9000
  • SMB
  • 2017-10-17
  • B220
  • 42000
  • SMB/DO-214AA
  • 2017-10-17
  • B2200
  • 9985
  • E-mail to me.IN STCOK
  • NEC
  • CDIP16
  • 2017-10-17
  • B2200
  • 33708
  • NEC
  • CDIP16
  • 2017-10-17

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