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Vendor: Intersil
Package Cooled: 05+
D/C: 0731


Functional Tests (In Freescale Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQ = 950 mA, Pout = 23 W Avg., f1 = 2112.5 MHz, f2 = 2122.5 MHz and f1 = 2157.5 MHz, f2 = 2167.5 MHz, 2 - carrier W - CDMA, 3.84 MHz Channel Bandwidth Carriers, ACPR measured in 3.84 MHz Channel Bandwidth @ 5 MHz Offset. IM3 measured in 3.84 MHz Channel Bandwidth @ 10 MHz Offset. Peak/Avg. = 8.5 dB @ 0.01% Probability on CCDF.


 Horizontal This output produces only true H pulses of nominal width 5µs. The leading edge is triggered from the leading edge Sync Output of the input H sync, with the same prop. delay as the composite sync. The half line pulses present in the input signal   during vertical blanking are eliminated with an internal 2H eliminator circuit.


MAIN MEMORY PAGE READ: A Main Memory Page Read allows the user to read data directly from any one of the 4096 pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. To start a page read, an opcode of 52H or D2H must be clocked into the device followed by 24 address bits and 32 dont care bits. The first two bits of the 24-bit address sequence are reserved bits, the next 12 address bits (PA11 - PA0) specify the page address, and the next ten address bits (BA9 - BA0) specify the starting byte address within the page. The 32 dont care bits which follow the 24 address bits are sent to initialize the read operation. Following the 32 dont care bits, additional pulses on SCK result in serial data being output on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the address bits, the dont care bits, and the reading of data. When the end of a page in main memory is reached during a Main Memory Page Read, the device will continue reading at the beginning of the same page. A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin.


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