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A28F200BR-TB datasheet

A28F200BR-T/B
2-MBIT (128K X 16, 256K X 8)
SmartVoltage BOOT BLOCK
FLASH MEMORY FAMILY

n Intel SmartVoltage Technology
¾ 5V or 12V Program/Erase
¾ 5V Read Operation
n Very High Performance Read
¾ 80 ns Max. Access Time,
¾ 40 ns Max. Output Enable Time
n Low Power Consumption
¾ Maximum 65 mA Read Current at 5V
n x8/x16-Selectable Input/Output Bus
¾ High Performance 16- or 32-bit
CPUs
n Optimized Array Blocking Architecture
¾ One 16-KB Protected Boot Block
¾ Two 8-KB Parameter Blocks
¾ One 96-KB Main Block
¾ One 128-KB Main Block
¾ Top or Bottom Boot Locations
n Hardware-Protection for Boot Block
n Software EEPROM Emulation with
Parameter Blocks
n Automotive Temperature Operation
¾ -40°C to +125°C
n Extended Cycling Capability
¾ 30,000 Block Erase Cycles for
Parameter Blocks
¾ 1,000 Block Erase Cycles for Main
Blocks


1.0 PRODUCT FAMILY OVERVIEW
This datasheet contains the specifications for the
automotive version of the 28F200BR family of boot
block flash memory devices.
This device continues to offer the same
functionality as earlier “BX” devices but adds the
capability of performing program and erase
operations with a 5V or 12V VPP. The A28F200BR
automatically senses which voltage is applied to
the VPP pin and adjusts its operation accordingly.
1.1 New Features in the
SmartVoltage Products
The new SmartVoltage boot block flash memory
family offers identical operation as the current
BX/BL 12V program products, except for the
differences listed below. All other functions are
equivalent to current products, including
signatures, write commands, and pinouts.
· WP# pin has replaced a DU pin. See Table 1
for details.
· 5V program/erase operation has been added
that uses proven program and erase
techniques with 5V ± 10% applied to VPP.
If you are designing with existing BX 12V VPP boot
block products today, you should provide the
capability in your board design to upgrade to these
new SmartVoltage products.
Follow these guidelines to ensure compatibilty:
1. Connect WP# (DU on existing products) to a
control signal, VCC or GND.
2. If adding a switch on VPP for write protection,
switch to GND for complete write protection.
3. Allow for connecting 5V to VPP instead of 12V,
if desired.
1.2 Main Features
Intel’s SmartVoltage technology provides the most
flexible voltage solution in the industry.
SmartVoltage provides two discrete voltage supply
pins, VCC for read operation, and VPP for program
and erase operation. Discrete supply pins allow
system designers to use the optimal voltage levels
for their design. For program and erase

5 ADVANCE INFORMATION

Savings (APS) feature which minimizes system
battery current drain, allowing for very low power
designs. To provide even greater power savings,
the boot block family includes a deep power-down
mode which minimizes power consumption by
turning most of the flash memory’s circuitry off.
This mode is controlled by the RP# pin and its
usage is discussed in Section 3.5, along with other
power consumption issues.
Additionally, the RP# pin provides protection
against unwanted command writes due to invalid
system bus conditions that may occur during
system reset and power-up/down sequences.
Also, when the flash memory powers-up, it
automatically defaults to the read array mode, but
during a warm system reset, where power
continues uniterrupted to the system components,
the flash memory could remain in a non-read
mode, such as erase. Consequently, the system
Reset pin should be tied to RP# to reset the
memory to normal read mode upon activation of
the Reset pin.
The byte-wide or word-wide input/output is
controlled by the BYTE# pin. See Table 1 for a
detailed description of BYTE# operations,
especially the usage of the DQ15/A-1 pin.
The 28F200 products are available in a
ROM/EPROM-compatible pinout and housed in
the 44-lead PSOP (Plastic Small Outline)
package.
Refer to the DC Characteristics Table, Section 5.2
for complete current and voltage specifications.
Refer to the AC Characteristics Table, Section
5.3, for read, program and erase performance
specifications.
1.3 Applications
The 2-Mbit boot block flash memory family
combines high-density, low-power, highperformance,
cost-effective flash memories with
blocking and hardware protection capabilities.
Their flexibility and versatility reduce costs
throughout the product life cycle. Flash memory is
ideal for Just-In-Time production flow, reducing
system inventory and costs, and eliminating
component handling during the production phase.

n Automated Word/Byte Program and
Block Erase
¾ Industry-Standard Command User
Interface
¾ Status Registers
¾ Erase Suspend Capability
n SRAM-Compatible Write Interface
n Automatic Power Savings Feature
¾ 1 mA Typical ICC Active Current in
Static Operation
n Reset/Deep Power-Down Input
¾ 0.2 μA ICCTypical
¾ Provides Reset for Boot Operations
n Hardware Data Protection Feature
¾ Program/Erase Lockout during
Power Transitions
n Industry-Standard Surface Mount
Packaging
¾ 44-Lead PSOP: JEDEC ROM
Compatible
n ETOX™ IV Flash Technology

 

 

operations, 5V VPP operation eliminates the need
for in system voltage converters, while 12V VPP
operation provides faster program and erase for
situations where 12V is available, such as
manufacturing or designs where 12V is already
available.
The 28F200 boot block flash memory family is a
very high-performance, 2-Mbit (2,097,152 bit) flash
memory family organized as either 256 Kwords
(131,072 words) of 16 bits each or 512 Kbytes
(262,144 bytes) of 8 bits each.
Separately erasable blocks, including a hardwarelockable
boot block (16,384 bytes), two parameter
blocks (8,192 Bytes each) and main blocks (one
block of 98,304 bytes and one block of 131,072
bytes) define the boot block flash family
architecture. See Figure 3 for memory maps. Each
parameter block can be independently erased and
programmed 10,000 times. Each main block can
be erased 1,000 times.
The boot block is located at either the top
(denoted by -T suffix) or the bottom (-B suffix) of
the address map in order to accommodate
different microprocessor protocols for boot code
location. The hardware-lockable boot block
provides complete code security for the kernel
code required for system initialization. Locking and
unlocking of the boot block is controlled by WP#
and/or RP# (see Section 3.4 for details).
The Command User Interface (CUI) serves as the
interface between the microprocessor or
microcontroller and the internal operation of the
boot block flash memory products. The internal
Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
program and erase operations, including
verifications, thereby unburdening the
microprocessor or microcontroller of these tasks.
The Status Register (SR) indicates the status of
the WSM and whether it successfully completed
the desired program or erase operation.
Program and erase automation allows program
and erase operations to be executed using an
industry-standard two-write command sequence to
the CUI. Data writes are performed in word or byte
increments. Each byte or word in the flash
memory can be programmed independently of
other memory locations, unlike erases, which
erase all locations within a block simultaneously.
The 4-Mbit SmartVoltage boot block flash memory
family is also designed with an Automatic Power

When the product is in the end-user’s hands, and
updates or feature enhancements become
necessary or mandatory, flash memory eliminates
the need to replace an assembly. The update can
be performed as part of routine maintenance
operation by relatively unsophisticated
technicians.
The reliability of such a field upgrade is enhanced
by a hardware-protected 16-Kbyte boot block. If
the protection methods are implemented in the
circuit design, the boot block will be
unchangeable. Locating the boot-strap code in this
area assures a fail-safe recovery from an update
operation that failed to complete correctly.
The two 8-Kbyte parameter blocks allow
modification of control algorithms to reflect
changes in the process or device being controlled.
A variety of software algorithms allow these two
blocks to behave like a standard EEPROM.
Intel’s boot block architecture provides a flexible
voltage solution for the different design needs of
various applications. The asymmetrically-blocked
memory map allows the integration of several
memory components into a single flash device.
The boot block provides a secure boot PROM; the
parameter blocks can emulate EEPROM
functionality for parameter store with proper
software techniques; and the main blocks provide
code and data storage with access times fast
enough to execute code in place, decreasing RAM
requirements.
1.4 Pinouts
Intel’s SmartVoltage boot block architecture
provides upgrade paths in every package pinout to
the 8-Mbit density. The 28F200 44-lead PSOP
pinout follows the industry standard ROM/EPROM
pinout as shown in Figure 2.
Pinouts for the corresponding 4-Mbit and 8-Mbit
components are also provided for convenient
reference. 2-Mbit pinouts are given on the chip
illustration in the center, with 2-Mbit and 8-Mbit
pinouts going outward from the center.

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