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A29040-70 datasheet

A29040 Series
512K X 8 Bit CMOS 5.0 Volt-only,
Uniform Sector Flash Memory

n 5.0V ± 10% for read and write operations
n Access times:
- 55/70/90/120/150 (max.)
n Current:
- 20 mA typical active read current
- 30 mA typical program/erase current
- 1 mA typical CMOS standby
n Flexible sector architecture
- 8 uniform sectors of 64 Kbyte each
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within
that sector
n Embedded Erase Algorithms
- Embedded Erase algorithm will automatically erase
the entire chip or any combination of designated
sectors and verify the erased sectors

General Description
The A29040 is a 5.0 volt-only Flash memory organized as
524,288 bytes of 8 bits each. The 512 Kbytes of data are
further divided into eight sectors of 64 Kbytes each for
flexible sector erase capability. The 8 bits of data appear
on I/O0 - I/O7 while the addresses are input on A0 to A18.
The A29040 is offered in 32-pin PLCC, TSOP, and PDIP
packages. This device is designed to be programmed insystem
with the standard system 5.0 volt VCC supply.
Additional 12.0 volt VPP is not required for in-system write
or erase operations. However, the A29040 can also be
programmed in standard EPROM programmers.
The A29040 has a second toggle bit, I/O2, to indicate
whether the addressed sector is being selected for erase,
and also offers the ability to program in the Erase Suspend
mode. The standard A29040 offers access times of 55, 70,
90, 120, and 150 ns, allowing high-speed microprocessors
to operate without wait states. To eliminate bus contention
the device has separate chip enable (CE ), write enable
(WE ) and output enable (OE ) controls.
The device requires only a single 5.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase

The host system can detect whether a program or erase
operation is complete by reading the I/O7 (Data Polling)
and I/O6 (toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array data
or accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The A29040 is fully erased when
shipped from the factory.

- Embedded Program algorithm automatically writes
and verifies bytes at specified addresses
n Typical 100,000 program/erase cycles per sector
n 20-year data retention at 125°C
- Reliable operation for the life of the system
n Compatible with JEDEC-standards
- Pinout and software compatible with single-powersupply
Flash memory standard
- Superior inadvertent write protection
n Data Polling and toggle bits
- Provides a software method of detecting completion
of program or erase operations
n Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data
from, or program data to, a non-erasing sector, then
resumes the erase operation
n Package options
- 32-pin P-DIP, PLCC, or TSOP(Forward type)

The A29040 is entirely software command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls
the erase and programming circuitry. Write cycles also
internally latch addresses and data needed for the
programming and erase operations. Reading data out of
the device is similar to reading from other Flash or EPROM
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times
the program pulse widths and verifies proper program
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm - an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin.

The hardware sector protection feature disables operations
for both program and erase in any combination of the
sectors of memory. This can be achieved via programming
The Erase Suspend feature enables the user to put erase
on hold for any period of time to read data from, or
program data to, any other sector that is not selected for
erasure. True background erase can thus be achieved.
Power consumption is greatly reduced when the device is
placed in the standby mode.


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