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Records matching criteria: 79601

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· EPM7512AEBC256-2

· EF3000A-ES/M79V010

· EPM3064ALI44-10

Description: Elantec, Inc. products are not authorized for and should not be used within Life Support Systems without the specific written consent of Elantec, Inc. Life Support systems are equipment intended to sup- port or sustain life and whose failure to perform when properly used in accordance wit...

Applications: Notes: 1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. ...

Features: (MAX2700/MAX2701 EV kit (Figure 3), VCC = +3.0V, TA = +25C, SHDN = GAIN_SET = VCC, X2_EN = GND, CEXT+ connected to CEXT-, PLO = -13dBm, FLO = 980MHz (MAX2700) and 1200MHz (MAX2701), PLNAIN = -30dBm, PRFIN = -25dBm, LNAIN and RFIN (single-ended input to balun) driven from 50Ω source, LNAO...

· EPM7128BTC100-4N

Vendor:ALTERA   Package Cooled:TQFP   D/C:07+   

Description: Once the feature is enabled, the data in the protected sec- tors can no longer be erased or programmed when input levels of 5.5V or less are used. Data in the remaining sec- tors can still be changed through the regular programming method. To activate the lockout feature, a series of six ...

Applications: Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns, or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parame...

Features: The narrow tuning range of the VCSO requires that the input reference frequency must remain suitable for the current look-up table selection. For example, when switching between Inverse FEC ratio and Non-FEC ratio look-up table selections (see Table 5 on pg. 3), the input reference freq...

· ECRHA090N11

· ELM7SH00MB567

· EN5335QI-T790

· ENV59D55F1

· E-TDA7511N

Vendor:ST   Package Cooled:QFP   D/C:06+   

Description: To further understand 82C37A operation, the states generated by each clock cycle must be considered. The DMA controller operates in two major cycles, active and idle. After being programmed, the controller is normally idle until a DMA request occurs on an unmasked channel, or a software ...

Applications: The MAX4667 has two normally closed (NC) switches, the MAX4668 has two normally open (NO) switches, and the MAX4669 has one NC and one NO switch that guarantee break-before-make operation. These switches operate from a +4.5V to +36V single supply or from 4.5V to 20V dual supplies. All digital...

Features: DESCRIPTION Designed for monitors and high performance TVs, the E-TDA7511NS vertical deflection booster is able to work with a flyback voltage more than the double of VS. The E-TDA7511NS operates with supplies up to 42V, flyback output up to 92V and provides up to 2App output current ...

· ECUE1H010CCQ

Description: Multi-Input Wake Up (on the 8-bit Port L) Brown out detector Analog comparator Modulator timer (High speed PWM for IR transmission) 16-bit multi-function timer supporting PWM mode External event counter mode Input capture mode 1024 bytes of ROM 64 bytes of RAM

Applications: A new clock doubler feature has been implemented in the Z80180/ECUE1H010CCQ/Z8L180 device that allows the program- mer to double the internal clock from that of the external clock. This provides a systems cost savings by allowing the use of lower cost, lower frequency crystals instead of ...

· EDZ/22B

Vendor:ROHM   Package Cooled:12000   D/C:07+   

· ET9666TX

Vendor:ST   Package Cooled:DIP   D/C:99+   

· ERWQ551LGC391MC60M

· EL2001AJ

Vendor:EL   Package Cooled:CDIP   D/C:07+   

Description: The discriminator allows the connection of a ceramic resonator or LC tank. A minimization of THD and adjustment of center frequency versus temperature can only be achieved by using a LC tank. This performs a temperature independent stop signal.

Applications: Notes: 7. The luminous intensity, I V, is measured at the peak of the spatial radiation pattern. 8. The dominant wavelength, ëd, is derived from the CIE Chromaticity diagram, and represents the perceived color of the device. 9. 1 /2 is the off-axis angle where the luminous intensity...

Features: • Wide frequency rangeC122.0MHz to 300.0MHz • User specified tolerance available • Case at electrical ground • Will withstand vapor phase temperatures of 253C for 4 minutes maximum • All metal, resistance weld, hermetically sealed package • High shock r...

· ESE18L61C

· ECUV1H020TN

· ELXQ181VSN182MA45S

· EP20K200EBI652-2

Vendor:ALTERA   Package Cooled:BGA   D/C:07+   

Description: Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub-1-V Operable Max tpd of 1.7 ns at 1.8 V Low Power Consumption, 20-µA Max ICC 8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100...

Applications: INput 1 and INput 2 (IN1 and IN2) respectively determine the state of the corresponding output drivers (OUT1 and OUT2) under normal operating conditions. When an input is high, its corresponding output is active ON, and when low is disabled OFF. IN1 and IN2 have internal active pullCdowns ...

Features: NOTES: (1) Test levels: (A) 100% tested at 25C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (2) Junction temperature = ambient for 25C guaranteed specifications. (3) Junction temperature...

· ECWU1C104JB5

Description: Synchronous rectification provides excellent efficiency at high power levels, where N- or P- type MOSFETs can be used. At lower power levels (between 10% and 20% of full load) where fixed frequency operation is required, low power mode is entered. This mode optimizes efficiency by cutting b...

Applications: By convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. The device that is controlling the bus is the master. The master is responsible for generating the clock signal for all operations. Any device on the bus...

Features: The MAX1755/MAX1756 are offered in the 6-pin SOT23 package and are specified over the -40C to +125C temperature range. For other temperature sensors with SMBus interfaces, refer to the MAX1617, MAX1618, MAX1668, and MAX1805 data sheets.

· ED1502

Description: Operating features include an on/off inhibit, output voltage adjust (trim), an output current limit, and over-temperature protection. Target applications include telecom, industrial, and general purpose circuits, including low-power dual-voltage systems that use a DSP, microprocessor,...

Applications: 4096 bits of read/write nonvolatile (NV) memory organized as 16 pages of 256 bits each Eight memory pages with individual 64-bit secrets and 32-bit read-only non rolling-over page write cycle counters Secrets are write-only and have their own individual write cycle counters On-chip 512-bit...

Features: Built-in 6502 8-bit CPU 2 MHz CPU operation frequency 4K bytes of ROM 128 bytes of SRAM One 8-bit programmable base timer with 1 - 256 µsec interval n 29 programmable bi-directional I/O pins n 3 LED direct sink pins with internal serial resistors

· ECUE1H240JPQ

· EN5038A

Description: instant visual indication if there are any issues with the wiring plant supporting operation at the desired speed. This includes physical wiring defects or channel conditions, such as excessive cable length, return loss, crosstalk, echo, and noise. Broadcoms remote cable management and di...

Applications: If an ADJ-bypass capacitor is used, the amplitude of the output ripple will be independent of the output voltage. If an ADJ-bypass capacitor is not used, the output ripple will be proportional to the ratio of the output voltage to the reference voltage:

Features: The EN5038A is a high-speed, 2GHz differential PECL/ECL 1:5 fanout buffer optimized for ultra-low skew applications. Within device skew is guaranteed to be less than 25ps over temperature and supply voltage. The wide supply voltage operation allows this fanout buffer to operate in 2.5V,...

· E11703A

· EP1210DC-2

Vendor:ALTERA   Package Cooled:DIP   D/C:92   

Description: Active-Low. Reset is asserted when VCC drops below VTH and remains asserted until VCC rises above VTH for the duration of the reset timeout period. The MAX6323 has a push-pull output and the MAX6324 has an open-drain output. Connect a pullup resistor from RESET to any supply voltage up to +6V.

Applications: Note 7: Because the Bus LVDS serial data stream is not decoded, the maximum frequency of the CHTST output driver could be exceeded if the data stream were switched to CHTST. The maximum frequency of the BUS LVDS input should not exceed the parallel clock rate.

Features: The IN terminal is a TTL-compatible digital terminal that is the input control signal for the drivers. The EP1210DC-2/48 have noninverting inputs; the EP1210DC-2/49 have inverting inputs. On the EP1210DC-2 and EP1210DC-2, a high on IN results in a high on HIGHDR. On the EP1210DC-2 and EP121...

· ER1K100QC208-2

Vendor:QFP   Package Cooled:QFP   D/C:2005   

· EP20K60EQC208-2XN

Vendor:ALTERA   Package Cooled:QFP-208   D/C:00+ advantage series   

Description: The EP20K60EQC208-2XN is a 6-bit digitally programmed feedback divider designed to work with TPS40090 multiphase controller or other controllers having 0.7-V internal reference to support VRM 10.x compliant power supplies. The EP20K60EQC208-2XN is designed to sup- port discrete DC/DC co...

Applications: The improved architecture of the DMUX facilitates interfacing with high-speed ADCs operating at up to 2.2 Gsps. No tuning of the delay between the data and clock paths should be necessary since the data and clock paths are internally matched over the fre- quency and specified temperature ra...

Features: Compatible with Ethernet II IEEE 802 3 10base5 and 10base2 (Cheapernet) 10 Mb s Manchester encoding decoding with receive clock recovery Patented digital phase locked loop (DPLL) decoder re- quires no precision external components Decodes Manchester data with up to g20 ns of jitter Loop...

· ERJ3EKF4R75V

· ERB21B5C2E3R0CDX1L

· EPF81500AQC240-4AA

Vendor:ALTERA   Package Cooled:1000   D/C:00+   

Description: AMDs products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMDs product could create a situat...

Applications: Hynix HYMD232646A(L)8-M/K/H/L series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules(DIMMs) which are organized as 32Mx64 high-speed memory arrays. Hynix HYMD232646A(L)8-M/ K/H/L series consists of eight 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pi...

Features: The Burst Write command is initiated by applying logic low level to CS , CAS and WE while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle th...

· ECEC2FP151BJ

· ECJZEB1E222M

· ECEA0JKN330

· ERTG2KGG202

· ERB32Q5C2H430GDX1

Vendor:MURATA   Package Cooled:SMD   D/C:08+   

· EE80C186XL25

Vendor:N/A   Package Cooled:INTEL   D/C:I/C?UPROC*80C186XL*PLCC   

Description: The MAX2700/MAX2701 are highly integrated direct downconversion (zero-IF) receivers designed for wide- band wireless local loop (WLL) systems operating in the 1.8GHz to 2.5GHz band. The MAX2700/MAX2701s zero-IF architecture eliminates the need for IF down- conversion stages and the use of an ...

Applications: This series of 500 W Transient Voltage Suppressors (TVSs) provides the highest level of Peak Pulse Power (PPP) in the industry for the DO-213AB size MELF package. These PPP levels offer protection from switching transients, induced RF, secondary lightning, as well as ESD or EFT where these dev...

Features: A) J-level: spec is 100% tested at +25C, sample tested at +85C. LC/MC-level: spec is 100% wafer probed at +25C. B) J-level: spec is sample tested at +25C. C) The output current sourced or sunk by the EE80C186XL25 can exceed the maximum safe output current.

· EEVMC0G101R

Vendor:PANASONIC   Package Cooled:SMD   D/C:07+08+   

· ECJ0EC1H1R5C

· EP2S180F1020C3

Description: Intel or Motorola Bus Select. When 16/68# pin is at logic 1, 16 or Intel Mode, the device will operate in the Intel bus type of interface. When 16/68# pin is at logic 0, 68 or Motorola mode, the device will operate in the Motorola bus type of interface.

Applications: C MIDI Control Processor C Synthesis C Compatible Effects: Reverb and Chorus C Microphone Echo Processing (Two Channels) C Programmable Spatial Effect or Four-channel Surround C 4-band Stereo Equalizer High-quality Synthesis C Maximum 48-voice Polyphony and Reverb/Chorus (34 if a...

Features: Together with the TEA7000, the EP2S180F1020C3 can be used to implement an indoor wireless link for audio applications (system specific). Together with an AV-compliant Bluetooth radio module, the EP2S180F1020C3 can be used to implement a Bluetooth wireless audio functionality.

· EPU-PGMA-DS-1

· ERB1885C2E160GDX5

Vendor:MURATA   Package Cooled:SMD   D/C:08+   

· ESM2633

Description: There are six basic serial interface timing modes that can be used with the device. These modes are determined by the speed of I/O CLOCK and the operation of CS as shown in Table 1. These modes are (1) a fast mode with a 10-clock transfer and CS inactive (high) between conversion cycles, (2...

Applications: The NCP1575 is a low voltage buck controller. It provides the control for a DC−DC power solution producing an output voltage as low as 0.980 V over a wide current range. It contains all required circuitry for a synchronous NFET buck regulator using the V2t control method to achieve ...

Features: DUTY CYCLE DEFINITION The ESM2633/HL/ML/NL has two PWM duty cycle outputs (x,y). The acceleration is proportional to the ratio T1/T2. The zero g output is set to 50% duty cycle and the sensitivity scale factor is set to 4% duty cycle change per g. These nominal values are affected by the...

· EKMH201LGB272MAC0M

· ELC0607RA-8R2K1R7-PF

· EEUFC1E122E

· EL2120

Description: The quiescent current increases only slightly at dropout (120 µA typical), which prolongs battery life. The LP2954 with a fixed 5V output is available in the three-lead TO-220 and TO-263 packages. The adjustable LP2954 is provided in an 8-lead surface mount, small outline package. ...

Applications: New Low Profile TSSOP−8 Package Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Diode Exhibits High Speed, Soft Recovery Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperatures

Features: Electrically isolated: DBC base plate 3500 VRMS isolating voltage Standard JEDEC package Simplified mechanical designs, rapid assembly Auxiliary cathode terminals for wiring convenience High surge capability Wide choice of circuit configurations Large creepage distances UL E78996 ...

· EKY-160ESS681MJ16S

· EP1800JC-2

Description: Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the IDT71V2546/48. (CE1 or CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle. The ZBTTM has a two cycle de select, i.e., the data bus will tri-state two clo ck...

Applications: DC Bias Block. The DC bias block provides voltage bias to the whole chip, which may be put in standby mode using the ENABLE digital input control pin (pin 6). The ENABLE pin is compatible with TTL levels. When the ENABLE pin is driven high, the device is enabled.

Features: Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the ADP3413 or ADP3418. Connecting the PWM3 and/or PWM4 outputs to GND will cause that phase to turn off, allowing the EP1800JC-2 to operate as a 2-, 3-, or 4-phase controller.

· EP1800JC2

Vendor:ALTERA   Package Cooled:800   D/C:00+   

· ELJPA1R0MF

Description: The RC32355 is a System on a Chip which contains a high perfor- mance 32-bit microprocessor. The microprocessor core is used exten- sively at the heart of the device to implement the most needed functionalities in software with minimal hardware support. The high performance microprocessor...

Applications: For this application, the derived voltage reading, Vd, is related to the actual instantaneous line voltage Vi by the expression, Vd = Vi Kd/Kv or Vi = Vd Kv/Kd, where Kd is the digitization constant for the ADC in this applica- tion and Kv is the voltage proportionality constant for the ...

Features: LO+, LO C (Pins 14, 15): Differential Local Oscillator In- puts. The ELJPA1R0MF works well with a single-ended source driving the LO+ pin and the LOC pin connected to a low impedance ground. No external 50Ω matching compo- nents are required. An internal resistor is connected across the...

· EKY-101ESS561MMN3S

· EPF10K50BI356-3N

Description: The TS7221 is amicropower comparator featuring rail to rail input performance in a tiny SOT23-5 package. This comparator is ideally suited to space and weight critical applications. It is fully specified at 2.7V, 5V and 10V operations over the industrial temperature range (-40/+85C).

Applications: Lock Time6 Frequency Pushing (Open Loop) Frequency Pulling (Open Loop) Harmonic Content (Second) Harmonic Content (Third) Output Power5, 7 Output Power5, 8 Output Power Variation VCO Tuning Range NOISE CHARACTERISTICS5 VCO Phase Noise Performance9

Features: Eight GLBs, 16 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock as shown in figure 1. The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. Each ispLSI 1048C device contains six Megablocks.

· EP20K100TC1442

· EP20K100TC144-2

Description: The HC164 and HCT164 are 8-bit serial-in parallel-out shift registers with asynchronous reset. Data is shifted on the positive edge of Clock (CP). A LOW on the Master Reset (MR) pin resets the shift register and all outputs go to the LOW state regardless of the input conditions. Two Seria...

Applications: Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V, control inputs only); I and Y pins do not contribute to ICC. 4. This ...

Features: • Packaged in 16 pin SOIC or TSSOP • Uses fundamental 10 - 27 MHz crystal, or clock • Patented PLL with the lowest phase noise • Output clocks up to 156 MHz at 3.3 V • Low phase noise: -132 dBc/Hz at 10 kHz • Output Enable function tri states outputs ...

· EXB28V470JX

Description: The CY7C4261/71/81/91V consists of an array of 16K, 32K, 64K, or 128K words of nine bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF, FF).

Applications: The filter response is flat to within 0.014 dB up to 0.21fs (e.g. 5.75MHz at a 27MHz clock rate), with stopband attenu- ation greater than 56dB above 0.29fs. Symmetric-coefficient filters such as the EXB28V470JX always have linear phase response. Half-band response ...

Features: This circuit uses a Darlington pair topology with resistive feedback for broadband performance as well as stability over its entire temperature range. Internally matched to 50 Ohm impedance, the EXB28V470JX requires only DC blocking and bypass capacitors for external components.

· EEUFC1E121E

· ELXZ160ELL562ML35S

· ECSH1DC106Y

· EEEHA1C471UP

Vendor:PANASONIC   Package Cooled:SMD   D/C:07+08+   

· EEE-HA1C471UP

Vendor:PANASONIC   Package Cooled:SMD   D/C:07+08+   

· EVQP6JB35

· EPMA506250000MC0EPMA506250000MC0EPMA506250000MC0

· EKZE160ELL102MJ20S

· EP2A70B724I8

Vendor:ALTERA   Package Cooled:BGA   D/C:08+   

· EWE6(AT33)

Vendor:N/A   Package Cooled:N/A   D/C:9+   

Description: IOAPIC clock output. (14.318 MHz) Poweredby VDDL CPU Output clocks. Powered by VDDL (60 or 66.6MHz) Free running CPU output clock. Not affected ty the CLK_STOP#. Freerunning IOAPIC clock output. Not affected by the CLK_STOP# (14.31818 MHz) Powered by VDDL

Applications: The addition of positive feedback (< 10 mV) is also recommended. It is good design practice to ground all unused pins. Differential input voltages may be larger than supply voltage without damaging the comparators inputs. Voltages more negative than C0.3 V should not be used.

Features: Pin to pin and functional compatible to National NS16C552 16 byte transmit FIFO 16 byte receive FIFO with error flags Modem control signals (CTS*, RTS*, DSR*, DTR*, RI*, CD*) Programmable character lengths (5, 6, 7, 8) bits Even, odd, or no parity bit generation and detection ...

· ELJFB820KF

Vendor:800000   Package Cooled:PANASONIC   D/C:09+   

· EP20K300ERC240-3XN

Vendor:ALTERA   Package Cooled:QFP240   D/C:03+/04+   

· ES1A_NL

· EL6282ES

· EEVTG1C222UM

Vendor:PANASONIC   Package Cooled:SMD   D/C:07+   

· EEV-TG1C222UM

Vendor:PANASONIC   Package Cooled:SMD   D/C:07+08+   

· EDMGR37KAF/CA51001-0121

Vendor:CASIO   Package Cooled:lcd   D/C:LCD   

· ECST1AZ335R

· EMLD500ADA330MHA0G

Vendor:NIPPON   Package Cooled:SMD   D/C:07+   

· EM78P468NQ

Description: n 5V output within 1.2% over temperature (A grade) n Adjustable 1.23 to 29V output voltage available (LP2954IM and LP2954AIM) n Guaranteed 250 mA output current n Extremely low quiescent current n Low dropout voltage n Reverse battery protection n Extremely tight line and load regul...

Applications: Output frequency range: 1050 MHz to 1250 MHz Divide-by-2 output 3.0 V to 3.6 V power supply 1.8 V logic compatibility Integer-N synthesizer Programmable dual-modulus prescaler 8/9, 16/17, 32/33 Programmable output power level 3-wire serial interface Analog and digital lock detect Hardwa...

Features: mode. IR indicates whether or not the FIFO has available memory locations. OR shows whether the FIFO has data available for reading or not. It marks the presence of valid data on the outputs. Each FIFO has a programmable Almost-Empty flag (AEA and AEB) and a programmable Almost-Full flag (A...

· EETHC2Q182KC

· ERO25MKF5101

Description: NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-spe...

Applications: 100% production tested at TA = +25C. Parameters over temperature are guaranteed by design. PWRGD_ asserts a time tPOR_HL after VPGTH12, VPGTH3.3, and VPGTH3.3AUX conditions are met. The UVLO for the 3.3V supply is sensed at 3.3SA+. This is the time that ON_ or AUXON_ must stay low when resetti...

Features: OTP The second section of memory consists of two 64-byte arrays, each writable only once. These arrays are always password protected. Reading from either of these arrays requires the use of an OTP Read password. Both arrays can be read with a single operation. Writing either array requi...

· EGXE100ESS472MLN3S

· EP7192SQC160-15

· ECEV1EA470WP

Vendor:PANASONIC   Package Cooled:SMD   D/C:07+08+   

Description: 1.1 Greece has waited for long for character 10/14, which is the Greek Question mark. The fact that it looks like the Latin semicolon is not an argument for not including this character into the G1 set. In many cases in a Greek text, the Greek Question Mark is the only thing a grammar che...

Applications: All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDD/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2. NOTE 3: Defined as skew between outputs on differe...

Features: The ECEV1EA470WP is not a modem chip but a complete modem including the telephone interface integrated into a compact module. It provides user transferable FCC Part 68 registration and can connect directly to the telephone line through an RJ11 jack. The modem connects to the host through...

· E07070KOA

Description: To retain data, 1024 refresh cycles are required in each 16 ms period. There are two ways to refresh the memory. 1. By clocking each of the 1024 row addresses (A0 through A9) with RAS at least once every 16 ms. Any read, write, read-modify-write or RAS-only cycle refreshes the ad- dre...

Applications: The transmission data is input from TX+/- pins differentially. In general, this differential signal is coupled through an AUI isolation transformer. In the MAU design, it is preferable that an equivalent 78 Ohm load be placed across these 2 pins for proper loading for the signal source. Imp...

Features: OSOP Series resistor networks feature a space saving 25 Mil lead pitch versus the current 50 Mil pitch standard. This allows users to reduce board space more than 50% over current standards. The OSOP Series feature 10 isolated resistors in a 20 lead style available for immediate delivery ...

· EKMR421VSN271MA25S

· EXBA10E104J

Description: A family of products offers 3-line, 2-line, and simple decod- ers in 8-bit and 10-bit versionsall in a pin and software- compatible format. Serial and parallel control ports are pro- vided. These submicron CMOS devices are packaged in a 100-lead Metric Quad Flat Pack (MQFP).

Applications: Pericom Semiconductors EXBA10E104J is a Rail-to-Rail Quad 2:1 multiplexer/demultiplexer LanSwitch with 3-state outputs. The On- Resistance typically varies from 5 ohms to 7 ohms with data inputs of 0V to 5V. Generally, this part can be used to replace mechanical relays in low voltage (3.3...

Features: Rail-to-Rail Input and Output Small SOT-23 Package Gain Bandwidth Product: 10MHz C40C to 85C Operation Slew Rate: 2.25V/µs Low Input Offset Voltage: 1.5mV Max High Output Current: 25mA Min Specified on 3V, 5V and 5V Supplies High Voltage Gain: 1000V/mV 10k Load High CMRR: 88dB Min ...

· EC3016NPAP

Vendor:CARLO GAVAZZI   Package Cooled:proximity switch   D/C:07+   

· EPF10K100ABC356

Vendor:ALTERA   Package Cooled:BGA   D/C:258   

Description: A write operation requires an 8-bit data word address following the device address word and acknowledg- ment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. After receiving the 8-bit data word, the EEPROM will output a zero...

Applications: Acknowledge Polling Since the device will not acknowledge during a write cycle , this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughout). Once the stop condition for a write command has been issued from the master, the device initiates th...

Features: The UCC3808 family offers a variety of package temperature range options, and choice of undervoltage lockout levels. The family has UVLO thresholds and hysteresis options for off-line and battery powered systems. Thresholds are shown in the table below.

· ECHS1H153GZW

Vendor:pan   Package Cooled:pan   D/C:dc04   

Description: BP_DIS is used to enable or disable the autoswitching function between bus-powered mode and self-powered mode. When BP_DIS is connected low and the voltage on SP is greater than the undervoltage-lockout (UVLO) threshold, the device will switch to self-powered operation automatically; if the...

Applications: AMBE-2000™ Vocoder Chip is a registered trademark of Digital Voice Systems, Inc. Other product names mentioned may be trademarks or registered trademarks of their respective companies and are the sole property of their respective manufacturers. All Rights Reserved Data subject to ch...

Features: Eight Independent Channel 14-Bit DACs with Output Amplifiers Low Power 320 mW (typ.) Parallel Digital Data and Address Port Double Buffered Data Interface Readback of DAC Latches Zero Volt Output Preset (Data = 10 .. 00) 14-Bit Resolution, 12-Bit Accuracy Extremely Well Matched DAC...

· EM51M256A-15P

Vendor:ETRONTECH   Package Cooled:2000   D/C:53   

Applications: * Under the constraint of the maximum frequency variation, (∆F/F)max, 1%, code 3, 7 (ceramic resonator option) must be selected while pins 39 and 40 are connected to a ceramic resonator. If (∆F/F)max, 10%, code 1, 5 (RC OSC option), then it is recommended to be selected. Also...

Features: Output Current 700 mA (Continuous per Output) Shoot-Through Current Protection Circuit PWM Control Input Frequency up to 200 kHz Built-In DC/DC Boost Converter Low Power Consumption Standby Mode Undervoltage Detection and Shutdown Circuit Pb-Free Packaging Designated by Suffix Code EV

· EX024B

Description: Line Build-Out, Transmitter: Logic low used with 225ft or more of cable is used on transmit path. Logic high used with less than 225ft of cable. DS3, E3 and STS-1 Select: Set low for E# applications. Set high for DS3, allow to float for STS-1 operation. Formerly OPT! on the 78P7200. Transmit...

Applications: Building on experience gained from previous generations of FPGAs, the Virtex family represents a revolutionary step forward in programmable logic design. Combining a wide variety of programmable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced proce...

Features: System overview Transponders Antenna Host system I/O functions Power supply Reader module software Reader module hardware Microcontroller Interface microcontroller to host Transmitting part Receiving part Digital signal processing unit Periodic disturbers Voltage regulating un...

· EEUFC1J221E

· EP310DM-1/883B

Vendor:ALTERA   Package Cooled:WCDIP20   D/C:04+/05+   

· ESMQ181VSN122MQ40S

· EN5312Q

Vendor:EN   Package Cooled:QFN   D/C:06+   

Description: Other features of the EN5312Q include two independent end-of-charge indications, including a digital indication that is programmable with a resistor-to-ground and an analog cur- rent output that is proportional to the output current, allowing for monitoring of the actual charging current....

Applications: o +2.7V to +5.5V Input Range o Output Voltages +0.4V to +3.4V Output at 600mA (Top Circuit) +1.5V Output at 600mA (Bottom Circuit) o Dynamically Variable Output Voltage (Top Circuit) o Adjustable Output Voltage Through Resistive Voltage-Divider (Bottom Circuit) o Internal Switch and...

Features: When calculating synchronous frequencies, use tS1 if all inputs are on dedicated input pins. The parameter tS2 should be used if data is applied at an I/O pin. If tS2 is greater than tCO1, 1/tS2 becomes the limiting frequency in the data path mode unless 1/(tWH + tWL) is less than 1/tS2.

· EVAL-ADF7020DB2

Vendor:ADI   Package Cooled:06+   D/C:500   

Description: The EVAL-ADF7020DB2 can perform conversions at rates of 15, 30, 60, or 240 samples per second (SPS). The onboard programmable gain amplifier (PGA), which offers gains of up to eight, allows smaller signals to be measured with high resolution. In single-conversion mode, the EVAL-ADF7020DB2...

Applications: These Intersil RS-485/RS-422 devices are BiCMOS 3.3V powered, single transceivers that meet both the RS-485 and RS-422 standards for balanced communication. Unlike competitive devices, this Intersil family is specified for 10% tolerance supplies (3V to 3.6V).

Features: The EVAL-ADF7020DB2 is a very low ROEVAL-ADF7020DB2 dual SPST analog switch. ROEVAL-ADF7020DB2 is a of 5 W (Typ) at 5.0 V. The device is offered in the very popular low cost US8 package. It is designed as a general purpose dual switch and can be used to switch either analog signals such as ...

· E-L4981AD013TR614

· EP20K60EQI240-2X

Vendor:ALTERA   Package Cooled:ALTERA   D/C:03+/04+   

Description: Wire-bond and flip-chip packages are available. Table 4 and Table 5 show the maximum possible number of user I/Os in wire-bond and flip-chip packages, respectively. Table 6 shows the number of available user I/Os for all device/pack- age combinations.

Applications: Antenna driver current is dimensioned, so as to guarantee that for Zant, within the specified range, the antenna driver can act as a perfect current source to drive the resonant circuit. For a typical Zant~L*Q = 1kOhm (e.g. L= 67uH, Q=19), and MODU at 1V, EP20K60EQI240-2X will force 4V antenna...

Features: The EP20K60EQI240-2X is a bipolar integrated circuit for use in mono portable and pocket radios. It is used when a minimum of perpheral components (of small dimensions and low costs) is important. The circuit contains a frequency-locked-loop(FLL) system with an intermediate frequency(IF) ...

· EL2006AG

Description: Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor- mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ...

Applications: The architecture of RDRAM devices allows the highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. The separate control and data buses with independent row and column control yield over 95% bus efficiency. The RDRAM device's 32 banks support up t...

Features: The EL2006AG also features Nationals 3D Sound circuitry which can be externally adjusted via a simple RC network. For maximum system flexibility, the EL2006AG has an exter- nally controlled, low-power consumption shutdown mode, and an independent mute for power and microphone ampli- fier...

· EVM7JSX30BY5

· ECQV1103JM9

· EPM8636ALC84-15

Vendor:ALTERA   Package Cooled:800   D/C:01+   

· EVK105CH2R7JW-F

Description: These miniature surface mount MOSFETs utilize Motorolas High Cell Density, HDTMOS process. Low rDS(on) assures minimal power loss and conserves energy, making this device ideal for use in small power management circuitry. Typical applications are dc−dc converters, power management ...

Applications: The onboard oscillator is designed to free run at approximately 19kHz at microampere current levels. The oscillator frequency is divided by 128 to provide the backplane frequency, which will be approximately 150Hz with the oscillator free-running; the oscillator frequency may be reduced by co...

Features: Six link ports provide for a second method of multiprocess- ing communications. Each link port can support communications to another EVK105CH2R7JW-F. Using the links, a large multiprocessor system can be constructed in a 2D or 3D fashion. Systems can use the link ports and cluster multip...

· ECHU1H151JB5

Vendor:PANASONIC   Package Cooled:0805-151   D/C:05+   

Description: The HYM72V64M636B(L)F8 is 64Mx64bits Synchronous DRAM Modules. The modules are composed of sixteen 32Mx8bits CMOS Synchronous DRAMs in FBGA package, one 2Kbit EEPROM in 8pin TSOP package on a 144pin glass-epoxy printed circuit board. One 0.1uF decoupling capacitor is mounted on the printed cir...

Applications: The AG302 is a general-purpose buffer amplifier that offers high dynamic range in a low-cost surface-mount package. At 900 MHz, the AG302 typically provides 15 dB of gain, +27 dBm Output IP3, and +13 dBm P1dB. The device combines dependable performance with consistent quality to maintain ...

Features: Software compilers support the three different global OLMC modes as different device types. Most compilers also have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to...

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