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· JANTX2N1978

· JX2N3235

· JDC-20-5

Description: NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf 0.25 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. The measurement of VOC(PP) is mad...

Applications: The PLL in JDC-20-5 clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT, FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]). JDC-20-5 is also able to track Spread Spectrum Clocking (SSC) for reduced E...

Features: The PGA is digitally controlled with 10-bit resolution on a linear dB scale, resulting in a gain range of 0dB to 36dB with 0.047dB per LSB of the gain code. The auto calibration circuit compensates for any inter- nal offset of the JDC-20-5 as well as black level offset from the CCD.

· JV2N1508

Description: To avoid artefacts in moving parts of the picture a motion detector is implemented to control the filter coefficient K according to detected changes between two adjacent fields. The motion detector performs a low pass filtering of the field differences and builds the absolute values. The re...

Applications: Figure 3 is a photograph of the various waveforms present- ed during this test Offset voltage and offset current are displayed at a sensitivity of 1 mV and 100 nA per division respectively and both parameters are displayed over a common mode range of g10V

Features: Refers to the voltage between the pin for which the compliance voltage is specified and GND. The pattern used is composed by a repetitive sequence of eight 1s followed by eight 0s at 10.7 Gbps. 3Measured using the high speed characterization circuit shown in Figure 3. 4The pattern used is ...

· J2N2612

· JTX2N710

· JX2N6332

Vendor:MOTOROLA   Package Cooled:TO-3   D/C:08+   

· JM54AC574BZA

· J2N6805

· JM38510/31004BDA

Vendor:TI   Package Cooled:DIP   D/C:NS   

Description: 1) CPD is defined as the value of the ICs internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + I CC/2 (per FLIP/ FLOP)

Applications: Diagonal 3mm (Type 1/6) 768 (H) 494 (V) approx. 380K pixels 811 (H) 508 (V) approx. 410K pixels 3.30mm (H) 2.95mm (V) 3.200µm (H) 3.725µm (V) Horizontal (H) direction: Front 3 pixels, rear 40 pixels Vertical (V) direction:Front 12 pixels, rear 2 pixels Horizontal ...

Features: The programming flowchart in Figure 3 shows the fast interactive programming algorithm. The interactive al- gorithm reduces programming time by using 50ms to 105ms programming pulses and giving each address only as many pulses as is necessary in order to reliably program the data. After each ...

· JANTX2N1799

· JV2N6305

Description: Input Zener Voltage Over Heating Protection Temperature Level Hysteresis IGBT Chips Over Heating Protec. Temp. Level Hysteresis Inverter Collector Current Protection Level DB Collector Current Protection Level Over Current Detecting Time Alarm Signal Hold Time Limiting Resistor for Alarm ...

Applications: 32-Bit Multiplexed Address/Data Programmable Memory Configuration Selectable 8-, 16-, 32-Bit Bus Widths Supports Unaligned Accesses Big or Little Endian Byte Ordering New Instructions Conditional Add, Subtract and Select Processor Management High-Speed Interrupt Controller 31 Progr...

Features: Interfaces 8 E1/T1/J1 ports UTOPIA Interfaces (level 1 and 2, ATMF AF-PHY 0017.000, 0039.000) - Line side 155 Mbit/s throughput, ATM device - Backplane side 622 Mbit/s throughput, Multi Phy device 16/32-bit Microcontroller Interface (Intel or Motorola type)

· JANTX2N5621

Description: A decode cycle begins immediately after the assigned re- ceive time-slot, and 10 µs later the Decoder DAC output is updated. The total signal delay is 10 µs plus 120 µs (filter de- lay) plus 62.5 µs (1⁄2 frame) which gives approximately 190 µs.

Applications: Functions To provide memory addresses. During sector erase A19-A11 address lines will select the sector. During block erase A19-A15 address lines will select the block. To output data during read cycles and receive input data during write cycles. Data is internally latched during a write...

Features: With USB connected, but without DC power, charge current is set to 100mA (max). This allows charging from both powered and unpowered USB hubs with no port communication required. When DC power is connected, charging current is set at 280mA (typ). No input-blocking diodes are required to preven...

· JANTX2N6600

· JPM2131-F008-7F

· JANTX2N6653

Description: SUPPLY VOLTAGE: 2.7 to 3.6V 128K x 16 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIME: 55ns SINGLE BYTE READ/WRITE LOW STANDBY CURRENT LOW VCC DATA RETENTION: 1.5V TRI-STATE COMMON I/O AUTOMATIC POWER DOWN PACKAGES C Compliant with Lead-Free Soldering Processes C Lead...

Applications: 1) Connect RF ports J1, J2 to RF test equipment. 2) Connect common ground terminal to the Ground (GND) pin on the board. 3) Connect logic control pin VL to positive supply. 4) Connect terminals VC1, VC2 and VC3 together and connect to positive supply (VC). 5) Connect terminals VM1, VM2 an...

Features: The JANTX2N6653/JANTX2N6653/JANTX2N6653 single/dual/quad comparators are optimized for low-power consumption while still providing a fast output response. They are designed for single-supply applications from 2.5V to 5.5V, but can also operate from dual supplies. These comparators have a 3&mi...

· JQX-115F-24VDC

Vendor:NAIS   Package Cooled:DIP   D/C:1999   

· JX2N3055

Description: -15 VIN - is the input for applying -15 volts to run the low power section of the hybrid. This pin should be connected to -15 VOUT if running off of the internal regulator. The re- quired bypassing of the -15 VOUT pin is sufficient in this case. For bringing in -15 volts, this pin should ...

Applications: Source Current Sink Current VID Input Threshold VID Pull-up Resistors Regulation Detect Comparator Input Offset Regulation Detect to EAOUT Delay BBFB to FB Bias Current Ratio VID 11111x Blanking Delay VID Step Down Detect Blanking Time VID Down BB Clamp Voltage VID Down BB Clamp Curr...

Features: Operating voltage: 2.4V~5.0V Directly drives an external transistor Low standby current (1mA typ. for VDD=3V) Minimal external components 508 words table ROM for key functions Programmable silence length and end-pulse width (minimal end-pulse width is 330ms at a 6kHz sampling rate) 8....

· J810-A2839

· JAN1N6060A

Description: VI(VSNS) = 1.5 V, EN = Low (IN1 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V, IO(OUT) = 0 A VI(VSNS) = 1.5 V, EN = Low (IN1 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V, IO(OUT) = 0 A VI(VSNS) = 0 V, EN = Low (IN2 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V, IO(OUT) = 0 A VI(VSNS) = 0 V, EN =...

Applications: FUNCTION The JAN1N6060A uses a silicon gate CMOS process to achieve low power consumption and high noise margin. The JAN1N6060A independently forms a 16-bit serial input-paral- lel output shift register and a parallel input-serial output shift register to read serial input data during ou...

Features: For wide input, dynamic range applications, the JAN1N6060A pro- vides two input ranges: high gain mode and low gain mode. A vernier 7-bit transconductance (Gm) stage provides 28 dB of gain range at better than 2 dB resolution, and 22 dB of gain range at better than 1 dB resolution. A seco...

· JTX2N6318

Vendor:MOT/MSC   Package Cooled:TO-66   D/C:07+   

· JV2N2896

Description: The use of Differential Rambus Signaling Level (DRSL) tech- nology permits 4000/3200/2400 Mb/s transfer rates while using conventional system and board design technologies. XDR DRAM devices are capable of sustained data transfers of 8000/6400/4800 MB/s.

Applications: suspend feature while erasing a sector when you want to read data from a sector in the other plane. After the erase suspend command is given, the device requires a maxi- mum time of 15 µs to suspend the erase operation. After the erase operation has been suspended, the plane which ...

· JX2N5616

Vendor:MOT   Package Cooled:TO-3   D/C:08+   

· JM54AC153B2A

· JANTX2N5606

Description: DESCRIPTION The VND5N07, VND5N07-1, VNP5N07FI and VNK5N07FM are monolithic devices made using STMicroelectronics VIPower M0 Technology, intended for replacement of standard power MOSFETS in DC to 50 KHz applications. Built-in thermal shut-down, linear current limitation and overvoltag...

Applications: The JANTX2N5606A also incorporates a low power Real-Time Clock (RTC) and two low power 16-bit counters. The RTC runs using a 32 kHz crystal oscillator and is register adjustable. The RTC and the counters are able to operate in all microcontroller modes. The instruction set is based on th...

Features: • Burst read/write operation and burst read/single write operation capability • Programmable burst length: 1/2/4/8/full page • 2 variations of burst sequence  Sequential (BL = 1/2/4/8/full page)  Interleave (BL = 1/2/4/8)

· JX2N2060B

· J2N3792

Vendor:MOT   Package Cooled:TO-3   D/C:08+   

· JH8901

· J2N569

· JX2N719

· JTS01-10LT10DI

Vendor:FIRECRON   Package Cooled:FIRECRON   D/C:QFP   

· JANTX2N5179A

Description: essors, but also eliminates bus contention in multiple bus microprocessor systems. An addi- tional feature of the HT23C256 is its ability to enter the standby mode whenever the chip en- able (CE/CE) is inactive, thus reducing current consumption to below 30µA. The combination of these ...

Applications: The DG308B/309B analog switches are highly improved versions of the industry-standard DG308A/309. These devices are fabricated in Vishay Siliconix proprietary silicon gate CMOS process, resulting in lower on-resistance, lower leakage, higher speed, and lower power consumption.

Features: Note 14: The JANTX2N5179A input and output voltage swings are limited by internal clipping. However, its ∆Ó topology is relatively tolerant of momentary internal clipping. The input clipping is tested with a crest factor of 2, while the output clipping is tested with a DC input. ...

· JANTX2N5103

Description: The ULN2001A, ULN2002A, ULN2003A, and ULN2004A are monolithic high-voltage, high-current Darlington transistor arrays. Each consists of seven npn Darlington pairs that feature high-voltage outputs with common-cathode clamp diodes for switching inductive loads. The collector-current rating of...

Applications: KS1454 is a DVDP (Digital Video Disc Player) 1-chip LSI which includes the digital servo and DSP(Digital Signal Processor) features. Servo Block performs the digital servo function, which controls disc speed and pick-up location as it retrieves signals from the disc (CD,VCD,DVD). Servo block ...

Features: Retry Counter The JANTX2N5103 contains a retry counter. The retry counter allows 8 accesses with an invalid password before any action is taken. The counter will increment with any combination of incorrect passwords. If the retry counter overflows, the memory area and both of the ...

· JAN2N4117A

Vendor:SILICONI   Package Cooled:CAN4   D/C:N/A   

· JAN2N6118

Vendor:MOTOROLA   Package Cooled:CAN3   D/C:07+   

Description: The MC33399 includes the 30kohm LIN pull-up so this does not need to be included on the PCB. The only discrete components required are pull-up resistors for the IRQ and Reset pins, decoupling capacitors and a crystal and its associated components. Two PortC pull-ups and a 9 volts zener circ...

Applications: • Excellent high frequency characteristics Isolation: Min. 60dB (at 1.5 GHz) Insertion loss: Max. 0.3dB (at 900 MHz) • V.S.W.R.: Max. 1.5 (at 900MHz) • High sensitivity in small size Size: 20.2 11.2 9.7 mm .795 .441 .382 inch Nominal power consumption: 200 mW (si...

Features: The JAN2N6118 is a clock generator that produces a spread-spectrum (dithered) square-wave output of fre- quencies from 130kHz to 66.6MHz. The JAN2N6118 is shipped from the factory programmed at a specific fre- quency and spread-spectrum percentage. The user still has access to an internal fre...

· JTX2N6305

· JANTX1N4465SOD64

· JAN2N2202

· JANTX2N2908A

· JM3851030007BCA

Description: Digital signal power supply : +5 V Selection of control method Digital input/output synchronization signal Digital input/output bit clock Serial control interface chip select signal Digital signal output Digital signal input Analog/digital input selection Digital input/output format sel...

Applications: The write operation is initiated by forcing #CE and #WE low and #OE high. The write procedure consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the device. Step 2 is an internal programming cycle, during which the data in the page buffers are...

Features: Vertical-dump speed. When VDS is high, the vertical-dump frequency is 2 MHz; when VDS is low, the vertical-dump frequency is 1 MHz. VDS can also function as a timer reset by dropping the voltage on VDS from VCC to VCC/2 and then raising it back to VCC.

· JM39015/1-007PPJM39015/1-007PPJM390151007PP

· J0011D01ENL

· JAN2N6105

· J2N6271

· JANTX2N48A

· JANTX2N6298

Applications: transferred into the serial shift register on the rising edge of the CLK pin. On the falling edge of the 8th clock the data in the serial shift register is latched into the parallel DAR register. The DAR remains powered up whenever VDD is present. The serial data is clocked into the DATA pin ...

Features: s 4M x 4-bit organization s EDO Page Mode for a sustained data rate of 50 MHz s RAS access time: 50, 60, 70 ns s Low power dissipation s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh, Hidden Refresh s Refresh Interval: 4096 cycles/64 ms s Available in 24/26-pin 300 mil...

· JANTX2N1241

· JQX-115F012-1ZS2

Description: hysteresis losses in an inductor, as well as ESR losses in capacitors, are the limiting factors in going to higher operating frequencies. Moreover, the effective impedance of capacitors and inductors at higher operating frequencies are dominated by ESL, ESR, and interlayer capacitance, wh...

Applications: The JQX-115F012-1ZS2 is optimized for CDMA handsets powered by single-cell Li-Ion batteries. Its high level of integration sig- nificantly reduces the design effort, number of discrete components, and solution size/cost. The main-sub LDO structure reduces the standby current consumption, ...

Features: The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the 2- wire interface. The programming is done at V CC supply only. Programming super voltages are generated inside the chip. See the Programming Specification for Atmel's Con- figuration ...

· JD54LS283BFA

· JAN2N2200

· JAN2N3638

· JAN2N1472

· JAPAN17505000

· JAN2N5475

Description:  SRAM • Power dissipation Operating : 40 mA Max Standby : 10 µA Max • Power down features using CE1s and CE2s • Data retention supply voltage: 1.5 V to 3.1 V • CE1s and CE2s Chip Select • Byte data control: LB (DQ7 to DQ0), UB (DQ15 to DQ8)

Applications: *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note:1. Linearity of the amplifier is calculated using a best fit method at three operating points of IOUT at 20 mA, 40 mA, and 60 mA. IOUT = (IIN GAIN) + IOS

Features: The JAN2N5475/JAN2N5475/JAN2N5475 are single/dual/ quad, low-cost, low-power comparators that consume only 2.8µA and provide a propagation delay, tPD, typi- cally 3µs. They have an operating-supply voltage from 2.5V to 5.5V when operating from a single supply and from 1.25V to 2.7...

· JMK113L

Vendor:JINGHUA   Package Cooled:/   D/C:/   

· JANTXV2N7218U

Vendor:IR   Package Cooled:SMD-1   D/C:00+   

Description: After determining which clock edge to use, a start and stop bit, appended internally, frames the data bits in the register. The start bit is always high and the stop bit is always low. The start and stop bits function as the embedded clock bits in the serial stream.

Applications: All inputs, outputs, and clock signals on the TMS551xx devices are compatible with Series 74 TTL. All address lines and data-in lines are latched on-chip to simplify system design. All data-out lines are unlatched to allow greater system flexibility.

Features: CS falling edge to first SCLK falling edge. SCLK logic high pulse width. SCLK logic low pulse width. Valid data setup time before falling edge of SCLK. Data hold time after SCLK falling edge. Minimum time between the end of data byte transfers. Minimum time between byte transfers during...

· JW150R1

Description: The MAX3221 consists of one line driver, one line receiver, and a dual charge-pump circuit with 15-kV ESD protection pin to pin (serial-port connection pins, including GND). The device meets the requirements of TIA/EIA-232-F and provides the electrical interface between an asynchronous comm...

Applications: The LPV321/358/324 are the most cost effective solutions for the applications where low voltage, low power operation, space saving and low price are needed. The LPV321/358/324 have rail-to-rail output swing capability and the input common-mode voltage range includes ground. They all exh...

Features: JW150R1EC ( GMAC ) is a general purpose single chip 10/100 Fast Ethernet controller. With no glue logic or very little extra logic, it can be used in a variety of system applications through its host bus interface. Single chip solution will help reduce system cost, not only on the IC cou...

· JM38510/31004B2A

Description: DESCRIPTION Transil diode arrays provide high overvoltage pro- tection by clamping action. Their instantaneous re- sponse to transient overvoltages makes them particularly suited to protect voltage sensitive de- vices such as MOS Technology and low voltage supplied ICs. The ITA series ...

Applications: Due to highly efficient magnetic circuit de- sign, leakage flux is reduced and changes in electrical characteristics from compo- nents being mounted close-together are minimized. This all means a packaging density higher than ever before. • Nominal operating power: 14...

Features: The RAM's working register area in data memory bank 0 is further divided into four register banks. Each register bank has eight 4-bit registers that are addressable either by 1-bit or 4-bit instructions. Paired 4-bit registers can be addressed as double registers by 8-bit instructions. Regi...

· JANTX2N6908

· JDV2S31SC

· JHP2601

· JS28F640J3A-120

Vendor:INTEL   Package Cooled:TSOP56   D/C:06+   

· JA3214-OS-AO4

Description: Data transmission for the DPSK mode requires that data ultimately be transmitted in a synchronous fashion. The 73K322L includes ASYNC/SYNC and SYNC/ASYNC converters which delete or insert stop bits in order to transmit data at a regular rate. In Asynchronous mode the serial data comes from th...

Applications: Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE)...

Features: In addition, for applications that program JA3214-OS-AO4 at the factory, Analog Devices offers device programming software2 running in Windows® NT, 2000, and XP operating systems. This software application effectively replaces any external I2C controllers, which in turn enhances users s...

· JANTX2N4896Z

· JSM1-12V-4

Description: 1. This drawing measure is a standard value. All dimensions are in millimeter. 2. In case of designation is tolerance 0.3mm. 3. Lead spacing is measured where the lead emerge from the package. 4. Protruded resin under flange 1.0mm Max. 5. Lens color: Black. 6. Above specification may b...

Applications: The digital inputs are CMOS-compatible and equipped with a built-in pull-up resistor with a typical rating of 85 kW to VCC. The input threshold totals VTH = 0.57 ´ VCC with a typical hysteresis of 100 mV. The inputs are designed for an input voltage of -0.2 V to VCC + 0.6 V.

Features: Introduction The JSM1-12V-4 is designed for multi-outputs applications. It includes two synchronous buck controllers and a lin- ear regulator controller. The two synchronous controller operates with fixed frequency voltage mode and can be configured as two independent controller or 2-phase co...

· JM38510/10304BG

· JANTX2N6695

· JM38510/30401BEA

Description: Parameter Relay Portion (Pins 15,16) Output Characteristics @ 25C Load Voltage, DC or Peak AC Load Current (Continuous) On-Resistance Off-State Leakage Current Switching Speeds Turn-On Turn-Off Output Capacitance Relay Portion (Pins 2,3) Input Characteristics @ 25C Input Control...

Applications: Level-triggered control input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes LOW, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock (unless SYNC ...

Features: Figure 1 and 2 are photographs of digitized waveforms showing a typical transient voltage and the clamping action of the JM38510/30401BEALC module. The device was sub- jected to a 2000A, 8/20µs impulse waveform in accor- dance with ANSI C62.36. The JM38510/30401BEA has an operating ...

· JAN1N4562B

Description: DSPCDSP Semaphore 0 DSPCDSP Semaphore 1 DSPCDSP Interrupt Reserved Reserved Reserved Reserved Register Bus Lock DSPCDSP Semaphore 0 DSPCDSP Semaphore 1 DSPCDSP Interrupt Reserved AC97 RegisterCPDC Bus Access Status PDC Interface Busy Status (write from DSP pending) Reserved Regist...

Applications: The PIC12C67X devices have 128 bytes of RAM, 16 bytes of EEPROM data memory (PIC12CE67X only), 5 I/O pins and 1 input pin. In addition a timer/counter is available. Also a 4-channel, high-speed, 8-bit A/D is provided. The 8-bit resolution is ideally suited for appli- cations requiring l...

Features: The JAN1N4562B/JAN1N4562B are ultra-low supply current, low-dropout linear regulators intended for low-power applications that demand the longest possible battery life. Unlike inferior PNP-based designs, the JAN1N4562B/ JAN1N4562Bs PMOS pass elements maintain an ultra-low 2µA supply cur...

· JRW017A0B8-66

Vendor:TYCO   Package Cooled:DIP   D/C:2006   

· JANTX2N5213

· JBS010-2000

Vendor:YAMAICHI   Package Cooled:N/A   D/C:05+   

· JANTX1N938B

Description: An active LOW Write Enable signal (WE) controls the writing/ reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A...

Applications: The RC5051 is a programmable synchronous DC-DC controller IC. When designed around the appropriate exter- nal components, this device can be configured to deliver more than 14.5A of output current. The RC5051 utilizes both current-mode and voltage-mode PWM control to create an inte...

Features: The JANTX1N938B and JANTX1N938B (high-density JANTX1N938BA Series) FPGA Configuration EEPROMs (configurators) provide an easy-to-use, cost-effective configuration mem- ory for programming Altera FLEX devices. The JANTX1N938BA Series is packaged in the popular 20-lead PLCC and the 32-lead TQ...

· JANTX2N1351

· JT-7051C-67

Vendor:PTC   Package Cooled:SOP20   D/C:03+   

Description: Provide a very well decoupled 5V bias supply for the IC to this pin by connecting it to the ATX 5VSB output. This pin provides all the bias for the IC as well as the input voltage for the internal standby 3V3AUX LDO. The voltage at this pin is monitored for power-on reset (POR) purposes.

Applications: The JT-7051C-67SXL programmable interval timer is compatible with the Intel 8254 programmable interval timer and contains three identical timers (CH0CCH2). CH0 and CH1 can be used to generate accurate timing delays under software con- trol. CH2 may be configured to provide a WATCHDOG time...

Features: Description Power Supply Terminal. The JT-7051C-67 will support supply voltages ranging from +2.7V to +5.5V. Ground Terminal. 2-Wire serial data interface. The serial data pin is for serial data transfer to and from the JT-7051C-67. The pin is open drain and may be wire-ORed with other open ...

· JWZ1120-0902

· JX2N2868

· JANTX2N4239L

· JANTX1N5554

Description: Clock output with programmable frequency (up to 48 MHz) Complies with the ACPI™, OnNow™ and USB power management requirements Internal power-on and low-voltage reset circuit, with possibility of a software reset Operation over the extended USB bus voltage range (4.0 V to 5.5...

Applications: Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic Inputs accept voltages up to 5 V Direct interface with TTL levels High noise immunity Complies with JEDEC standard: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8B/JES...

Features: SYNC (Pin 9): Driver Synchronization Input. 0V at this pin forces both ME and MF high after an initial negative pulse. A subsequent positive pulse at SYNC input forces ME to pull low, whereas a negative pulse forces MF to pull low. The SYNC signal should alternate between positive and negativ...

· JRC0026

Vendor:JRC   Package Cooled:SOP3.9mm   D/C:1995   

Description: • Cambie las pilas del control remoto cuando el televisor comienza a no reaccionar a sus comandos. • Presione la extremidad de la tapa y tire de la misma para tener acceso al compartimento de las pilas. • Observe la polaridad de las pilas (+ y -). • Use solamente p...

Applications: The quickest path to understanding the PSoC silicon is by read- ing this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an over- view of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For...

Features: NOTE: 6. This specification relates to the clock frequency range over which the JRC0026(A) will correctly perform its various functions. See the Max Clock Frequency section under Component Value Selection for limitations on the clock frequency range in a system.

· JM38510/35101BFA

· JANTXS2N4013A

Description: I/O performance is increased to 622 Mb/s using Source Synchronous data transmission architectures and synchro- nous system performance up to 240 MHz using sin- gled-ended SelectI/O technology. Additional I/O standards are supported, notably LVPECL, LVDS, and BLVDS, which use two pins pe...

Applications: ICCSupply currentVCC = MAX,All outputs disabled5270mA † All typical values are at VCC = 5 V, TA = 25C, and VIC = 0. ‡ The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for threshold levels only. No...

Features: The LM87 is a highly integrated data acquisition system for hardware monitoring of servers, Personal Computers, or virtually any microprocessor-based system. In a PC, the LM87 can be used to monitor power supply voltages, moth- erboard and processor temperatures, and fan speeds. Ac- tual...

· J1011F01PNL793

· JG82852GMESL8D7

Description: VDDID Strap:see Note 4 Notes: 1. DQ-to-I/O wiring may be changed within a byte 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ/DQS resistors should be 22 Ohms. 4. VDDID strap connections(for memory device VDD, VDDQ); Strap out :(open) : VDD=VDDQ Strap In (Vss) :...

Applications: This document contains advance information for the JG82852GMESL8D7 microprocessor,includingelectrical characteristics and package pinout information. Detailed functional descriptions other than parametric performance are published in the i960® Jx Microprocessor Users Guide (272483).

Features: DoCD™ Debug Unit C its a real-time hard- ware debugger provides debugging capability of a whole SoC system. In contrast to other on- chip debuggers DoCD™ provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any co...

· JANTX2N3217

· JANTX2N362

Description: When redundant instructions such as LD A,#im and LD EA,#imm are used consecutively in a program sequence, only the first instruction is executed. The redundant instructions which follow are ignored, that is, they are handled like a NOP instruction. When LD HL,#imm instructions are used consecu...

Applications: Regulation is measured at constant junction temperature using low duty cycle pulse testing. Parts are tested for load regulation in the load range from 0.1mA to 150mA. Changes in output voltage due to heating effects are covered by the thermal regulation specification. Ground pin current is...

Features: The AS2885 offers full protection against over-current faults, reversed input polarity, reversed load insertion, and positive and negative transient voltage. On-Chip trimming adjusts the reference voltage to 1%. The IQ of this device flows into load, which increases efficiency.

· JX2N2532

· JC082C33V34M8

Vendor:jauch   Package Cooled:jauch   D/C:dc03   

Description: outdoor displays optical indicators signal and symbol luminaire marker lights (e.g. steps, exit ways, etc.) lighting for special effects (e.g. starry sky) substitute for miniature flashlight furniture lighting (e.g. glass cupboards)

Applications: Drain-to-Source Breakdown Voltage Gate Threshold Voltage# ➃ Gate-to-Source Leakage Forward Gate-to-Source Leakage Reverse Zero Gate Voltage Drain Current Static Drain-to-Source# ➃ On-State Resistance (TO-3) Static Drain-to-Source# ➃ On-State Resistance (TO-254AA) Diod...

Features: The JC082C33V34M8/MAX6626 feature a shutdown mode that saves power by turning off everything but the power-on reset and the I2C-compatible interface. Four separate addresses can be configured with the ADD pin, allowing up to four JC082C33V34M8/MAX6626 devices to be placed on the same bus. Th...

· J2N4053

· JM3852001601BCBJM3852001601BCBJM3852001601BCB

· JX2N1974

· JANTX2N6181

· J2N551

· JANTX2N1711

Description: Memories C 8K dual voltage High Density Flash (HDFlash) or ROM with read-out protection capability. In- Application Programming and In-Circuit Pro- gramming for HDFlash devices C 384 bytes RAM C HDFlash endurance: 100 cycles, data reten- tion: 20 years at 55C Clock, Reset And Supp...

Applications: C Correlated Double Sampling (CDS) C Programmable Black Level Clamping Programmable Gain Amplifier (PGA) C6-dB to 42-dB Gain Ranging 12-Bit Digital Data Output: C Up to 28-MHz Conversion Rate C No Missing Codes 77-dB Signal-To-Noise Ratio Portable Operation: C Low Voltage: 2.7 V to 3.6 V...

Features: The HS-1135RH is a radiation hardened, high speed, low power current feedback amplifier built with Intersils proprietary complementary bipolar UHF-1 (DI bonded wafer) process. They are QML approved and processed in full compliance with MIL-PRF-38535. This amplifier features u...

· JANTX2N1099A

· JAN2N1265

· JAN2N926

Description: The device contains two operational amplifiers and a precision shunt regulator. OPAMP 1 is designed for voltage control, whose non-inverting input internally connects to the ouput of the shunt regulator. OPAMP 2 is for current control with both inputs uncommitted. The IC offers the powe...

Applications: Device supply =+5.0 VDC +/- 5% regulated. The JAN2N926 requires 11mA max. average that includes brief 50mA peak currents. When used, LEDs, pull-up resistors, and drivers require additional current from the +5VDC supply. An electrolytic and ceramic capacitor between (or very close to) both V...

Features: JAN2N926he JAN2N926, JAN2N926 and JAN2N926 single channel MICROCOUPLERS™ are all Pb-free, low profile miniature surface mount optocouplers in a Ball Grid Array (BGA) package. Each consists of an aluminum gallium arsenide (AlGaAs) infrared emitting diode driving a silicon phototr...

· JANTX2N2976

Description: Shutdown. When SHUTD input is low, the internal clock is stopped and the outputs are placed in a high-impedance state (three stated). When SHUTD input is high, the device is in normal operation. During continuous mode of operation, the recommended use of SHUTD is to first assert STOP input, ...

Applications: A collision occurs when two or more transmitters simultaneously transmit on the transmission media. A collision is detected by comparing the average DC level of the transmission media to a collision threshold. The received signal at RXI is buffered and sent through a low pass filter, th...

Features: The JANTX2N2976 is a current feedback operational amplifier using a very high speed complementary technology to provide a bandwidth up to 410MHz while drawing only 4.1mA of quiescent current. With a slew rate of 940V/µs and an output stage optimized for driving a standard 100͐...

· JANTX2N4998

· JKO-0036NL177

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