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Records matching criteria: 44427

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· NLCV32T-331K-PF-330UH

Vendor:TDK   Package Cooled:3225   D/C:08+   

· N760120CFKC103

Description: The NE5532, NE5532A, SA5532, and SA5532A are high-performance operational amplifiers combining excellent dc and ac characteristics. They feature very low noise, high output-drive capability, high unity-gain and maximum-output-swing bandwidths, low distortion, high slew rate, input-protection...

Applications: Using NFS gives great flexibility to the developer for controlling, debugging, and analyzing the target system from the host. This application note describes how to build an NFS for a Linux target on a Linux host system, how to download kernels from a host to a target, and how to start the...

Features: Case: SC-59, Molded Plastic Case material - UL Flammability Rating 94V-0 Moisture sensitivity: Level 1 per J-STD-020A Terminals: Solderable per MIL-STD-202, Method 208 Terminal Connections: See Diagram Marking: Date Code and Marking Code (See Diagrams & Page 2) Weight: 0.008 grams (app...

· NTMD2C02R2G

Vendor:ON   Package Cooled:SOIC-8 Narrow Body   D/C:08+   

Description: Featuring high performance word program, the SST39VF160Q/VF160 devices provide a maximum word-program time of 10 µsec. The entire memory can typically be erased and programmed word by word in 7 seconds, when using interface features such as Toggle Bit or Data# Polling to indicate ...

Applications: The NTMD2C02R2GD digital charge-transfer (QT) QMatrix™ IC is designed to detect touch on up to 32 keys in a scanned X-Y matrix. It will project the keys through almost any dielectric, like glass, plastic, stone, ceramic, and even most kinds of wood, up to thicknesses of 5 cm or more. T...

Features: !GENERAL DESCRIPTION The NTMD2C02R2G is a super small-sized package single C-MOS comparators with open drain output. The operating voltage is from 1V to 5.5V, and the interface can be connected with most of TTL and C-MOS type standard logic ICs. Furthermore, The input offset voltage is ...

· NJM2902V(TE2)

Description: The third overtone mode is not necessarily at exactly three times the fundamental frequency. The mechanical properties of the quartz element dictate the position of the overtones relative to the fundamental, and in a VCXO circuit, the third overtone is not typically exactly three times ...

Applications: Outputs of the NJM2902V(TE2) to the digital system ASIC are: transmit clock, receive clock, receive data, and five status lines: collision detect, carrier detect, jabber indication, duplex (half / full), and auto- negotiation (active / inactive).

Features: Single Byte/Single Cycle Code Execution The efficiency is due to the fact that the majority of instruc- tions are of the single byte variety, resulting in minimum pro- gram space. Because compact code does not occupy a sub- stantial amount of program memory space, designers can integrate ...

· NR6012T101M

· NMP7507

Description: 2.3 Order of precedence. In the event of a conflict between the text of this specification and the references cited herein, the text of this document takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained.

Applications: 8-bit Resolution 500 Msps (min) Sampling Rate Power Consumption: 3.8W Typ 500 mVpp Differential or Single-ended Analog Inputs Differential or Single-ended 50Ω ECL Compatible Clock Inputs ECL or LVDS/HSTL Output Compatibility ADC Gain Adjust Data Ready Output with Asynchronous Reset G...

· NRC10F10R0TR

Vendor:SMD/DIP   Package Cooled:SN   D/C:500   

Description: The receive data is determined by the data bus differential signal after a barrier transmission delay (tRZL). When the difference between the A input and the B input (A-B) is greater than +200mV, the R output will be HIGH. If A-B is more negative than C200mV, the R output is undefined. S...

Applications: The NRC10F10R0TR is a multi-chip PLL receiver device supplied in an SO20 package. It has been specially developed for the demands of RF low-cost data transmission systems with low data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. The receiver is well suited to operate with...

Features: The NRC10F10R0TR series can provide local on-card regulation, eliminating the distribution problems associated with single point regulation. Each employs internal current limiting, thermal shut-down and safe operating area protection, making it essen-tially indestructible. If adequate heat sink...

· NCP15WM154F0SRC

Vendor:MURATA   Package Cooled:0402   D/C:08/ROHS   

· NG82915P

Vendor:BGA   Package Cooled:Intel   D/C:05+   

Description: Product Description/Features: • Low skew, low jitter PLL clock driver • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • With bypass mode mux • Operating frequency 60 to 140...

Applications: Link Fault Indicator. This output indicates the status of the input data stream (RIN). It is controlled by three functions; the Carrier Detect (CD) input, the internal Transition Detector, and the Out of Lock (OOL) detector. The Transition Detector determines if RIN contains enough transitio...

Features: The 24xx128 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The bus must be con- trolled by a master device which generates the serial clock (SCL), co...

· NV393I

· NJU-7081V

Description: Buffer addressing is referenced in the datasheet using the terminology BFA8 - BFA0 to denote the nine address bits required to designate a byte address within a buffer. Main memory addressing is referenced using the terminology PA11 - PA0 and BA8 - BA0 where PA11 - PA0 denotes the 12 addres...

Applications: Output voltage is set to a nominal value between 26V and 28V, by an internal resistor network, but can be adjusted to lower values by external resistors, an external PWM control signal applied to the Enable pin, or a combination of the two. Depending upon the control frequency, the PWM s...

Features: 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems Table 2-0007/3448 by tester ground degradation. Guaranteed but not 100% tested. 2. Measured using 28 16-bit counters. 3. Typical values are at VCC = 5V and TA= 25C. 4. Maximum I...

· NCP1601APG

Vendor:ON   Package Cooled:DIP-8/-40~125    D/C:06+/07+   

Description: mode with little power consumption. It can also operate with high speed system clock rate of 3.58MHz in normal mode for high performance operation. To ensure smooth dialer function and to avoid MCU shut-down in extreme low voltage situation, the dialer I/O circuit is built-in to generate hard...

Applications: O.S. Polarity The O.S. output can be programmed via the con- figuration register to be either active low (default mode), or active high. In active low mode the O.S. output goes low when triggered exactly as shown on the O.S. Output Temperature Response Diagram, Figure 1. Active high simply i...

Features: The NCP1601APG is an integrated memory device containing a low power 8 Mbit Static Random Access Memory organized as 524,288 words by 16 bits. The base design is the same as NanoAmps standard low voltage version, NCP1601APG512W16. The device is fabricated using NanoAmps advanced CMOS process...

· NT71675FG-00053

Vendor:NOVATK   Package Cooled:0741+   D/C:QFP   

· NJU7660V(TE1)

Vendor:JRC   Package Cooled:SSOP   D/C:2002   

Description: Intel and Pentium are registered trademarks of Intel Corporation. Lexmark is a trademark of Lexmark International, Inc. Non-linear spread spectrum modulation profile is licensed under US Patent No. 5488627, Lexmark International, Inc. This document contains information on a preproduction produ...

Applications: NOTES: 4. The NJU7660V(TE1) stop pulse is two or three clocks in duration. 5. There may be none, one, or more idle states during the stop frame. 6. When the NJU7660V(TE1) is in continuous mode, there are 17 idle states between the stop frame and the start frame.

Features: The radiation hardened NJU7660V(TE1)RH is a low dropout adjustable negative regulator with an output voltage range of -2.25V to -26V. The device features a 1A output current capability, an adjustable current limit pin (ILIM) and a shutdown pin (SD) for easy on/off control.

· NSAM265SFB/V

Vendor:NATIONAL   Package Cooled:PLCC-68P   D/C:01+   

Description: • The use of twin crossbar contacts en- sures high contact reliability. AgPd contact is used because of its good sulfide resistance. Adopting low-gas molding material. Coil assembly molding technology which avoids generating vola- tile gas from coil. • Increased packa...

Applications: The LX1910 PWM buck regulator achieves very high efficiencies over a broad range of operating load conditions. The LX1910 implements a load-detection architecture and enters a power-saving PFM mode when driving small load currents ensuring optimal regulator efficiency over the enti...

Features: The NSAM265SFB/V features a serial interface and software protocol allowing operation on a popular two wire bus. The bus signals are a clock Input (SCL) and a bidirectional data input and output (SDA). Access to the device is controlled through a chip select (CS) input, allowing any num...

· NJM2360AD

Vendor:JRC   Package Cooled:DIP-8   D/C:06+   

Description: RSENSE - This is the common connection for the bot- tom of the bridge. This can have a sense resistor con- nection to the V+ return ground for current limit sens- ing, or can be connected directly to ground. The maxi- mum voltage on this pin is 2 volts with respect to GND.

Applications: Memory Interface • 16-bit EDO-DRAM or FPM-DRAM interface. • Memory size options: 512K bytes using one 256K16 device. 2M bytes using one 1M16 device. • Addressable as a single linear address space. CPU Interface • Supports the following interfaces: Hitachi ...

Features: The direction and value of current are programmable for each phase via separate control inputs. In the case of low at all four current program inputs the device is switched to inhibit mode automatically. A common oscillator generates the timing for the current control and turn-on with phase...

· NCV7001DW

Vendor:ON   Package Cooled:SOP-24   D/C:04+   

Description: The SN65LV1023A and SN65LV1224A are a 10-bit serializer/deserializer chipset designed to transmit data over differential backplanes or unshielded twisted pair (UTP) at clock speeds from 10 MHz to 66 MHz. The chipset has five states of operation: initialization mode, synchronization mode, da...

Applications: Atmel can accept Register Transfer level (RTL) designs for VHDL (MIL-STD-454, IEEE STD 1076) or Verilog-HDL format. Atmel fully supports Synopsys for VHDL simula- tion as well as synthesis. Design via VHDL or Verilog- HDL is the preferred method of performing a gate array design.

Features: The HYS64Dxx0x0GDL are industry standard 200-pin 8-byte Small Outline Dual in-line Memory Modules (DIMMs) organized as 64M x 64. The memory array is designed with Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial pre...

· NLC322522T-121K

Description: These devices consist of four 2-input digital multi- plexers with common select and strobe inputs. The HCT158 is an inverting multiplexer while the HCT157 is a non-inverting multiplexer. When the STROBE input is held High, selection of data is in- hibited and all the outputs become Low ...

Applications: o 4 Dedicated Comparators plus 1 Auxiliary Comparator o 5V Dedicated Comparator Has 1.25% Accuracy o -5V, +12V, -12V, +15V, -15V Dedicated Comparators Have 1.5% Accuracy o Overvoltage/Undervoltage Detection or Programmable Delay Using Auxiliary Comparator o Internal 1.24V Reference ...

Features: The NLC322522T-121K has a two-wire serial interface designed for data transfer operations, and is used for programming the P and Q values for frequency generation. Sclk is the serial clock line controlled by the master device. Sdata is a serial bidirectional data line. The NLC322522T-121K...

· NTCDS30183HG202GCN0

· NS62172

Vendor:NS   Package Cooled:CAN3   D/C:99+   

· NFM18PC105R0J3D

Description: Keep the output leads as short as possible. In the video frequency range, even a few inches of wire have significant inductance, raising the interconnection impedance and limit- ing the output current slew rate. Furthermore, the skin effect increases the resistance of heavy wires at high...

Applications: The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing ...

Features: The NFM18PC105R0J3D is set for a gain of 38.5 boosting the 2.33V signal to 90V. The recommended compensation for gains above 30 is used. If capacitive loading is at least 330pF at all times, the recommended snubber network may be omitted. The 27 ohm resistor sets current limit to a nomin...

· NE615N220

· NSD800D

· N74F538N6029N74F538N6029N74F538N6029

· NLCV32T-680K-PF-68UH

Vendor:TDK   Package Cooled:3225   D/C:08+   

· NJM2320RD5

Description: It should be remembered that a watchdog timer cannot detect a fault instantaneously. By definition, the watchdog timer must reach the end of its timeout interval before it resets the processor. The system designer should be aware of the maximum time interval that can occur between the executi...

Applications: The receiver section performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit wide parallel data to the recovered clock (Rx_CLK). It then extracts the 18 bits of data from the 20-bit wide data resulting in 18 bits of parallel data at the receive data ...

Features: The system may select the NJM2320RD5, move the wiper, and deselect the device without having to store the lat- est wiper position in nonvolatile memory. The wiper movement is performed as described above; once the new position is reached, the system would the keep INC LOW while taking C...

· N643HT6K1

· NRD211C107R12

Applications: Reading from the device is accomplished by enabling the chip (CE1, CE2, and CE3 LOW) while forcing the Output Enable (OE) LOW and Write Enable (WE) HIGH. If the first Byte Enable (BA) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If ...

Features: FEATURES NRD211C107R12: 550 MHz/1.2 GHz NRD211C107R12: 550 MHz/2.0 GHz NRD211C107R12: 1.0 GHz/2.7 GHz NRD211C107R12: 1.0 GHz/3 GHz 2.7 V to 5.5 V Power Supply Separate Charge Pump Supply (VP) Allows Extended Tuning Voltage in 3 V Systems Programmable Dual Modulus Prescaler RF and IF: 8/...

· NCP1001P120

· NH82801GB/SL8FX

Vendor:INTEL   Package Cooled:BGA   D/C:04+   

Description: s Fully programmable character formatting: x 5, 6, 7, or 8-bit characters x Even, Odd, or No-Parity formats x 1, 11⁄2, or 2-stop bit x Baud generation (DC to 5 Mbit/s) s False start-bit detection s Complete status reporting capabilities s 3-State output TTL drive capabilitie...

Applications: 1.70 (43.18mm) PCB Height 168-Pin Registered DIMM with Double Sided ECC support One 0.22µF and one 0.0022µF decoupling capacitors adopted Serial Presence Detect with Serial EEPROM Two Register Buffers & one Inverter used (with PLL) Supports Flow-through or Register mode by ...

Features: The DS1258 devices are shipped from Dallas Semiconductor with the lithium energy sources disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VTP, the lithium energy source is enabled for battery backup operation.

· NJM4565M-TE2

Description: This familiy is a 64Mbit dynamic RAM organized 16,777,216 x 4 bit configuration with Fast Page mode CMOS DRAMs. Fage page mode offers high speed of random access memory within the same row. The advanced circuit and process allow this device to achieve high performance and low power dissipatio...

Applications: • Dual Voltage Detection and Reset Assertion Low Vcc Monitor Low V2MON Monitor Low Vcc Block of EEPROM Writes RESET Signal Valid down to Vcc=1V • Selectable Watchdog Timer 150ms, 450ms, 1s, 5s, 10s, 20s, 1min, OFF • Volatile Flag shows Watchdog/Low Voltage Reset &#...

Features: Data transfers from the SRAM to the EEPROM (the STORE opera- tion), or from the EEPROM to the SRAM (the RECALL ) operation) are initiated through software sequences. The NJM4565M-TE2 combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. Onc...

· N74F195N-D

Description: Members of the Texas Instruments Widebus ™ Family 3-State True Outputs Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC ™ (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Lat...

Applications: There is one variable gain amplifier in each channel of the receiver. This amplifier is a two stage amplifier with gain from -20dB up to 45dB. Pins A2, A1 and A0 control the gain of the amplifier. The amplifier needs an external capacitor connected between the emitters of the first diffe...

Features: The reference voltage supplied to the N74F195N-D determines the analog input range. With a 4V reference, the analog input range is 3.2V differential biased around a common mode of 2V. This common mode biasing can be achieved using the on-chip differential amplifiers, further reducing the ...

· NCP301HSN23TG

Vendor:ON   Package Cooled:08+   D/C:SOT23-5   

· NLS201208T-2N0D

Description: The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register con- tents serve as inputs to an internal state-machine that controls the erase and programmi...

Applications: accumulator or multiple multiplier array. One, two, and three-pass algorithms are supported. For each output point in a typical two-dimensional single-pass static image filter, the NLS201208T-2N0D implements a spiralling pixel resampling algo- rithm, walking around the resampling ne...

Features: • PLL clock distribution optimized for SSTL_2 DDR SDRAM applications. • Distributes one differential clock input pair to five differential clock output pairs. • Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2 • Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2 • External feedba...

· NCV8504PWADJR2

Vendor:ON   Package Cooled:SOP/16   D/C:0450+   

Description: C1 Commutation Capacitor Negative Terminal. C2 Commutation Capacitor Positive Terminal. C2 Commutation Capacitor Negative Terminal. Doubling Inverting Charge Pump Output (C2 x VIN). Ground. Positive Power Supply Input. C1 Commutation Capacitor Positive Terminal. Inverting Charge Pump...

Applications: The ISL6118 has two shutdown modes. When disabled with a load current less than the current regulation (CR) level the ISL6118 shuts down in a controlled manner using a 500nA constant current source controlled ramp. When disabled during CR or if the timer has expired the ISL6118 quickly pulls ...

Features: The NCV8504PWADJR2 2-line to 4-line decoder is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When used...

· ND26VS18165CJ-6

Description: * On products compliant to MIL-PRF-38535, this parameter is not production tested. ¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedan...

Applications: LOW QUIESCENT CURRENT: 300µA DESIGNED FOR RS-485 INTERFACE APPLICATIONS -7V TO 12V COMMON MODE INPUT VOLTAGE RANGE DRIVER MAINTAINS HIGH IMPEDANCE IN 3-STATE OR WITH THE POWER OFF 70mV TYPICAL INPUT HYSTERESIS 30ns PROPAGATION DELAYS, 5ns SKEW OPERATE FROM A SINGLE 5V SUPPLY...

Features: The DS1258W 3.3V 128k x 16 Nonvolatile SRAM is a 2,097,152-bit, fully static, nonvolatile (NV) SRAM, organized as 131,072 words by 16 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry, which constantly monitors VCC for an out-of-tolerance condition. When such ...

· N74F544N300N74F544N300N74F544N300

· N74F543DT3N74F543DT3N74F543DT3

· NM93S46EM8

Vendor:NS   Package Cooled:NS   D/C:06+   

· NLP-2400+

· NVS3045

· NCP15WM154

Vendor:Murata   Package Cooled:402   D/C:09+   

· NN514260J

· NJM2123V-TE2-ZZZB

· NJM431U-TE1/4A

Description: The product identification mode can be used to identify the device and the manufacturer by hardware or soft- ware operation. The hardware operation mode is acti- vated by applying a 12.0 Volt on A9 pin, typically used by an external programmer to select the right program- ming algorithm ...

Applications: Turbo codes improves a transmission link by an additional gain of 2 to 3 decibels, compared to classical FEC solutions. TC3000 is a family of IP Cores offering powerful and flexible turbo product codes. TC3000 is the first IP Core implementing Hamming and double-error-correcting BCH product ...

Features: Dimensions - 2N6786 Inches Millimeters Min Max Min Max 0.101 0.111 2.55 2.81 0.104 0.108 2.64 2.74 0.071 0.081 1.81 2.07 0.074 0.078 1.88 1.98 0.020 0.030 0.50 0.76 0.023 0.027 0.58 0.69 0.0...

· NTCG063EH300K

· N588C50MA

· NFW31SP206X1E4

Vendor:Murata   Package Cooled:1206   D/C:09+   

· NRC10F22R1TR10

Vendor:SMD/DIP   Package Cooled:SN   D/C:500   

Description: cleared immediately, and remains cleared. If the power is restored (no UVREG or UVREF), and if no OVERTEMP fault exists, then the latched fault remains cleared when the RESET line returns to high. However, FAULT = 1 may still occur because a UVBOOT fault condition may still exist.

Applications: Electrostatic discharge can cause damage ranging from perfor- mance degradation to complete device failure. Burr-Brown Corpo- ration recommends that all integrated circuits be handled and stored using appropriate ESD protection methods.

Features: The CBTS3253 is a dual 1-of-4 high-speed TTL-compatible FET multiplexer/demultiplexer. The low on resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise.

· ND9945

· NJU2074D

Vendor:JRC   Package Cooled:STK   D/C:08+   

· NOLSIA

· NE5200D

Vendor:SOP8   Package Cooled:16890   D/C:PHILIPS   

Description: The function of the configuration unit is to transmit decompressed data to the FPGA, depending on the configuration scheme. The enhanced configuration device supports four concurrent configuration modes, with n = 1, 2, 4, or 8 (where n is the number of bits that are sent per DCLK cycle on ...

Applications: SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A17). The Address Inputs select the cells in the memory array to access dur- ing Bus Read operations. During Bus Write opera- t...

Features: The Hynix NE5200D Series are Dual In-line Memory Modules suitable for easy interchange and addition of 128Mbytes memory. The Hynix NE5200D Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the ...

· NEC2532350

· NCV85032

Vendor:ON   Package Cooled:2000   D/C:07+   

· NL322522T-5R6J(3225-56UH)

· NCP3418ADG

Vendor:3950   Package Cooled:ON   D/C:05PB   

Description: Low voltage operation (VCC/VDD: 2.7 to 3.6 V) Ultra-low power consumption (0.5 mW/ch at VCC = 3 V) Ultra-compact space-saving package lineup (SSOP-20) Contains 12-channel R-2R type 8-bit D/A converter On-chip analog output amps (sink current max. 1.0 mA, source current max. 1.0 mA) Analo...

Applications: The DS15433 constantly monitors the battery voltage of the internal batter. The Battery Low Flag (BLF) bit of the Flags register (B4 of 1FF0h) is not writable and should always be a 0 when read. If a 1 is ever present, an exhausted lithium energy source is indicated and both the contents of...

Features: • Single-Supply Operation (+2V to +6V) • Rail-to-Rail Analog Signal Dynamic Range • Low On-Resistance (6Ω typ. with 5V supply) Minimizes Distortion and Error Voltages • On-Resistance Flatness, 3Ω typ. • Low Charge Injection Reduces Glitch Errors...

· NYT3429

Vendor:FCI   Package Cooled:08+   D/C:10000   

· NT1818

Vendor:FCI   Package Cooled:08+   D/C:10000   

· NG82355SZ576

Description: The ADSP-21991 supports an additional external memory called I/O memory space. The IO space consists of 256 pages, each containing 1024 addresses. This space is designed to support simple connections to peripherals (such as data convert- ers and external registers) or to bus interface ASI...

Applications: The QS3VH16244 HotSwitch is a 16-bit high band bus switch. The QS3VH16244 has very low ON resistance, resulting in under 250ps propa- gation delay through the switch. The switches can be turned ON under the control of the LVTTL-compatible xG signal for bidirectional data flow with no ad...

Features: The receivers double-conversion architecture requires careful frequency planning. Besides the desired RF input signal, there are a number of spurious signals that may cause an undesired response at the output. Among them are the image of the RF signal (that must be suppressed by the RF front-...

· NH82801IH/SLA9P

Vendor:INTEL   Package Cooled:BGA   D/C:07+   

· NEC1679

Description: CioA or B portVCC = 5 V,16 † All typical values are at VCC = 5 V, TA = 25C. ‡ For I/O ports, the parameters IIH and IIL include the off-state output current. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

Applications: • All parameters specified for +5V single supply or 2.5V dual supply systems • Rail-to-rail input and output voltage ranges • Unity gain stable • Extremely low input bias currents -- 1.0pA • High source impedance applications • Dual power supply 1.0...

Features: Ref input is 5V tolerant 4 pairs of programmable skew outputs Low skew: 185ps same pair, 250ps all outputs Selectable positive or negative edge synchronization: Excellent for DSP applications Synchronous output enable Input frequency: 6MHz to 200MHz Output frequency: 6MHz to 200MHz 2x...

· NFM60R00T102T

Description: Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of Electrical Characteristics specify conditions for device operation.

Applications: The NFM60R00T102T keeps a constant 1.2V between the VFB pin and ground pin. By placing a resistor R1 across these two pins a constant current flows through R1, adding to the NFM60R00T102TFB current and into the R2 resistor producing a volt- age equal to the (1.2/R1)3R2 + NFM60R00T102TFB3R2 whi...

Features: The readout register has 2072 stages, with a further 18 extra stages at each end. What- ever the chosen transfer direction for the useful pixels, the 18 extra pixels, the 7 dark references and the 5 isolations are always transferred to the nearest output as shown in the figure hereunder.

· NM25C020EM8

· N80C188EB12

· NACE100M35V5X5.5TR13F

Vendor:NIC   Package Cooled:SMD   D/C:07+   

· NACZF102M35V18X17TR13T2F

Vendor:NIC   Package Cooled:SMD   D/C:07+   

· NLC565050T-6R8K

Vendor:TDK   Package Cooled:SMD   D/C:08+   

Description: These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance...

Applications: Programming of each output occurs through an industry- standard, two-wire serial interface. Unlike existing programmable buffers, the BUF12800 offers a high- speed, two-wire interface mode that allows clock speeds up to 3.4MHz. The BUF12800 features a double-buffered DAC register struct...

Features: The NLC565050T-6R8K is a synthesiser circuit fabricated on the GPS CMOS process and is capable of achieving high sideband attenuation and low noise performance. It contains a reference oscillator, 11-bit programmable reference divider, digital and sample-and-hold comparators, 10-bit progr...

· NLV32-101J-PF

Vendor:MURATA   Package Cooled:06+   D/C:200554    

· NEC1042

· NMC0603X7R683K16TRFNIC

· NJM072M

Description: Appendix B: Manual/Compatibility Mode Demodulator Write and Read Registers for Manual/Compatibility Mode DSP Write and Read Registers for Manual/Compatibility Mode Manual/Compatibility Mode: Description of Demodulator Write Registers Automatic Switching between NICAM and Analog Sound Func...

Applications: at 25C and 100C. Increasing the reverse bias will give some improvement in device blocking capability. The sustaining or active region voltage requirements in switching applications occur during turnCon and turnCoff. If the load contains a significant capacitive component, high current ...

Features: Notes: 4. CX1 must be placed within 0.7 cm of the HSDL-3612 to obtain optimum noise immunity. 5. In "HSDL-3612 Functional Block Diagram" on page 1 it is assumed that Vled and VCC share the same supply voltage and filter capacitors. In case the 2 pins are powered by different suppl...

· NL27WZ06DTT1G

Vendor:ON   Package Cooled:SOT164   D/C:2008+   

Description: International Rectifier's FRED.. series are the state of the art Ultra fast recovery rectifiers specifically designed with optimized performance of forward voltage drop and ultra fast recovery time. The planar structure and the platinum doped life time control, guarantee the best overall perfo...

Applications: Small and thin 4 mm 4 mm 1.45 mm LFCSP package 3 mg resolution at 50 Hz Wide supply voltage range: 2.4 V to 6 V Low power: 350 µA at VS = 2.4 V (typ) Good zero g bias stability Good sensitivity accuracy X-axis and Y-axis aligned to within 0.1 (typ) BW adjustment with a single c...

Features: The NL27WZ06DTT1G5E is a 3V-powered EIA/TIA-232 and V.28/V.24 communications interface with low power requirements, high data-rate capabilities, and en- hanced electrostatic discharge (ESD) protection. All transmitter outputs and receiver inputs are protected to 15kV using IEC 1000-4-2 Air-Ga...

· NLC423232T-1R8K-PF

· NX29F010-45PL

Description: A MEMSIC accelerometer is most sensitive to changes in position, or tilt, when the accelerometers sensitive axis is perpendicular to the force of gravity, or parallel to the Earths surface. Similarly, when the accelerometers axis is parallel to the force of gravity (perpendicular to the E...

Applications: The HYM72V32M656T8 Series are 32Mx64bits Synchronous DRAM Modules. The modules are composed of eight 32Mx8bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 144pin glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling ca...

Features: The NX29F010-45PLM integrates 64K words of on-chip memory configured as 32K words (24-bit) of program RAM, and 32K words (16-bit) of data RAM. Power-down circuitry is also provided to reduce power consumption. The NX29F010-45PLM is available in 144-lead LQFP and 144-ball mini-BGA packages.

· NMC27C64Q-150

Vendor:NS   Package Cooled:02+   D/C:3200   

Description: Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups....

Applications: NOTE 1. ICC1, ICC3, ICC4 and ICC6 dependent on output loading and cycle rates(tRC and tHPC). 2. Specified values are obtained with outputs unloaded. 3. ICC is specified as an average current. In ICC1, ICC3, ICC6, address can be changed only once while /RAS=VIL. In ICC4, address can be chan...

Features: Technology Corporation product best suited to the customer's application; they do notconvey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. Renesas Technology Corporation assumes no responsibility for an...

· NMC27C64Q150

Description: Serial Mode Operation Three CMOS compatible signals control the attenuator in this mode: DATA, CLK and LE. When LE is high the latch is enabled and data in the serial shift register gets loaded. When the LE is low the data in the shift register is latched. Refer to Figure 2 for the tim- ing d...

Applications: † Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. E...

Features: The NMC27C64Q150 CPLDs are supported by industry standard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Syn- opsys, Synario, Viewlogic, and Synplicity), using text (ABEL, VHDL, Verilog) and/or schematic entry. Design ver- ification uses industry standard simulators for functional and...

· NFM41R10C102T1M00338

· NF570LT-U-N-A3

Vendor:BGA   Package Cooled:nVIDIA   D/C:05+   

· NJM2337BH

Description: Differential current outputs are provided to support single- ended or differential applications. The current outputs may be directly tied to an output resistor to provide two complemen- tary, single-ended voltage outputs. The output voltage compliance range is 1.25 V.

Applications: • New specifications • Dual frequency standard for inductance value • Supports high temperature reflow soldering (260C, 3 times) • Surface mounting applicability (Supports both reflow and flow soldering) • High reliability (ceramic integrated structure, and t...

· NG8292SX

· NECUPD78F0511

Vendor:NEC   Package Cooled:experiment board   D/C:08+   

· NT7108

Vendor:n/a   Package Cooled:n/a   D/C:04+   

· NSC831E-3M

· NFR21GD4701012L

Description: The 32 registered macrocells in the GLB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each macrocell contains a programmable XOR gate, a pro- grammable register/latch/toggle flip-flop and the necessary clocks and control logic to allow combinatorial or registered operat...

Applications: When the Output Enable Input (E0) is HIGH, the outputs are forced to a high impedance off state. If the outputs are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enab...

Features: As shown in Figure 1-3, each transceiver channel in NFR21GD4701012L contains a serializer, a deserializer, an 8b/10b encoder and decoder, as well as elastic buffers that provide the interface for serial data transmission and data recovery. Both the receive equalization and the transmit pre-emp...

· NM802LQ

· NR99150SRI

Vendor:PERKINELMER   Package Cooled:n/a   D/C:08+   

· NJM2130

Description: ADV/LD is a synchronous input that is used to load the inte rnal registers with new address and control when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/LD is sampled high then...

Applications: Note 2: When non−modulated signal (optical all high or all low level signal) is inputted, output signal is unstable. When modulated optical high level signal is received, output signal is high. When modulated optical low level signal is received, output signal is low. The duty factor...

Features: The NJM2130 will wake-up upon detecting a button press and delay approximately 10 ms for button debounce (Figure 2-2). The synchronization counter, discrimination value and button information will be encrypted to form the hopping code. The hopping code portion will change every transmis...

· NTCG064BH202K

· NLV25T-120J

· NHI-1502

Description: Notes: 1. Worst case values occur at an IC junction temperature of 125C. 2. For designers who do not need to read from the display, the Read line can be tied to VDD and the Write and Chip Enable lines can be tied together. 3. Changing the logic levels of the Address lines when CE = &quo...

Applications: The GS82032 is a 2,097,152-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications ranging from DS...

Features: The product information available by this search method contains an overview of each product only. To search for data sheets containing more detailed product information, please visit the CISC Microcomputers page at the following URL and click on Data Sheets at the left-hand part of this page.

· NFM3DCC223R1H3L

Vendor:MURATA   Package Cooled:1206-3P   D/C:O7+   

Description: It is not necessary to have a host and target system that are the same architecture. Using cross-tools, any architecture can be used to develop PowerPC tools. The disadvantages to such an arrangement are never serious, but in general, inconvenient.

Applications: Thick metal clad ground planes restrict the thermal expansion of the dielectric substrates in the X-Y axis. The expansion of the dielec- tric will then be mainly in the Z axis, which does not affect the beam lead device. An alternate solution to the problem of dielec- tric ground plane exp...

Features: Thermistor : Temperature dependant resistor. Basically there are 2 types. The types that increase their resistance with rising temperature are PTC ( positive thermal coefficient ) types. The ones that decrease their resistance with rising temperature we call NTC ( negative thermal coef...

· NTMFS4849NT1G

· N82S23F

Description: Due to highly efficient magnetic circuit de- sign, leakage flux is reduced and changes in electrical characteristics from compo- nents being mounted close-together are minimized. This all means a packaging density higher than ever before. • Nominal operating power: 14...

Applications: • 1024 Resistor Taps C 10-Bit Resolution • SPI Serial Interface for write, read, and transfer operations of the potentiometer • Wiper Resistance, 40Ω Typical @ 5V • Four Non-Volatile Data Registers • Non-Volatile Storage of Multiple Wiper Positions •...

Features: • Function, pinout, and drive compatible with FCT and F logic • FCT-C speed at 5.2 ns max. (Coml) FCT-A speed at 6.5 ns max. (Coml) • Reduced VOH (typically = 3.3V) versions of equivalent FCT functions • Edge-rate control circuitry for significantly improved...

· NC7WZ17P6X_NF042

· NSEB

Description: This device is designed for Ethernet 100 Mbps and Intra-Office Telecom applications and offers an excellent price/performance ratio for cost effective solutions. Its double-lens optical system results in optimum coupling of power into the fiber.

Applications: The LOOP feature can also be used in applications where clock and data recovery are to be performed from either of two data streams. In these systems the LOOP pin is used to select whether the TSER or the RIN inputs are used by the Re- ceive PLL for clock and data recovery.

Features: settled to its final value, the NSEBA/ NSEBA and NSEBL/NSEBL monitor the voltage drop across the MOSFET. If the voltage drop exceeds the circuit breaker threshold the NSEBA/NSEBA and NSEBL/NSEBL turn off the MOSFET, discon-

· NL322522T-R82K-3

Description: Luminance bandwidth Chrominance bandwidth (Extended B/w mode) Chrominance bandwidth (Reduced B/w mode) Burst frequency (NTSC) Burst frequency (PAL-B, D,G,H,I) Burst frequency (PAL-N Argentina) Burst cycles (NTSC and PAL-N) Burst cycles ( PAL-B, D, G, H,I) Burst envelope rise / fal...

Applications: If the magnetic field exceeds the threshold levels, the current source switches to the corresponding state. In the low current consumption state, the current source is switched off and the current consumption is caused only by the current through the Hall sensor. In the high current cons...

· NM93C46AN

Vendor:fsc   Package Cooled:fsc   D/C:dc01   

Description: CIRCUIT OPERATION The SP8480 is a complete 8-channel data acqui- sition systems (DAS), with on-board multi- plexer, voltage reference, sample-and-hold, clock and tri-state outputs. The digital control archi- tecture is very similar to the industry-standard 574-type A/D, and uses identi...

Applications: Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage...

Features: the device has a Sector Group Protect function which hardware write protects selected sector groups. The sector group protect and unprotect features can be enabled in a PROM programmer. Temporary Sector Unprotect, which requires a high voltage, allows in-system erasure and code changes...

· NTCG203NH153JT1

Vendor:TDK   Package Cooled:0805   D/C:08/ROHS   

· NDP706113

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