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· OE627C10THN62321APRF7

Vendor:HIT   Package Cooled:PDIP32   D/C:9403   

· ORBIT6642A

Vendor:N/A(regular supply)   Package Cooled:PQFP-100   D/C:99   

Description: OUTPUT TRANSISTOR Collector-emitter Voltage BVCEO SFH600-0,1,2,3,4 SFH601-1,2,3,4,5 SFH609-1,2,3,4,5 Collector-base Voltage BVCBO SFH600-0,1,2,3,4 SFH601-1,2,3,4,5 SFH609-1,2,3,4,5 Emitter-collector Voltage BVECO Power Dissipation

Applications: If after 480 µs of low time the I/O line did not return high, either the I/O line has been shorted to ground or there is at least one 1Cwire device connected to the I/O line which is issuing an alarm interrupt (see Figure 6). In this case the DS1481 waits for I/O to return high for...

Features: The ORBIT6642A is a dual, high frequency MOSFET driver, specifically designed to drive N-Channel power MOSFETs in a synchronous-rectified buck converter. These drivers, combined with a Fairchild Multi-Phase PWM controller and power MOSFETs, form a complete core voltage regulat...

· OEC9001

Description: These two blocks accept signals from the REF inputs (REFA+, REFAC, REFB+, or REFBC) and the FB inputs (FBKA+, FBKAC, FBKB+, or FBKBC). Correction information is then generated to control the frequency of the voltage-controlled oscillator (VCO). These two blocks, along with the VCO, form ...

Applications: Each DAC has a high-impedance differential current output, suitable for single-ended or differential analog-output configurations. External resistors allow scaling the full-scale output current for each DAC separately or together, typically between 2 mA and 20 mA. An accurate on-chip voltag...

Features: Because of the serial data transfer, the OEC9001 iButton employs three address registers, called TA1, TA2 and E/S (Figure ??). Registers TA1 and TA2 must be loaded with the target address to which the data will be written or from which data will be sent to the 1-Wire master upon a Read comma...

· OCS35

Vendor:OKI   Package Cooled:DIP6   D/C:00+   

Description: RIN=30Ω, CIN=10µF, RL=499Ω, unless otherwise specified. Clamp Gate Input=0V, VCONTRAST=VDRIVE=VBRIGHTNESS=4V. Guaranteed by design but not tested. Typical parameters are representative of actual device performance but are for reference only. Industrial grade devices shall be...

Applications: 2. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL C...

Features: The SNOCS35 is designed using low-power techniques in a BiMOS technology. In most applications, the receivers contained in these devices interface to single inputs of peripheral devices such as ACEs, UARTs, or microprocessors. By using sampling, such peripheral devices are usually insensiti...

· OPA2680N

Description: The CP3BT10 connectivity processor is complete micro- computer with all system timing, interrupt logic, program memory, data memory, I/O ports included on-chip, making them well-suited to a wide range of embedded applications. The block diagram on page 1 shows the major on-chip com- pone...

Applications: 1. Externally detect a write to the low-power address. You select this address which can be any address in the 16 Mbyte addressing range of the MC68SEC000. A write to the low-power address can be detected by polling A23CA0, R/W, and FC2CFC0. When the low-power address is detected, R/W is ...

Features: The OPA2680N is a charge-pump based white-LED driver that is ideal for mobile phone display backlighting. It can drive up to 7 LEDs in parallel with up to 20mA through each LED. Regulated internal current sources deliver excellent current and brightness matching in all LEDs. The LED-drive...

· OPA2228UA/2K5E4

Vendor:TI   Package Cooled:SOP8   D/C:05+   

Description: Notes: a. Room = 25_C, Full = as determined by the operating temperature suffix. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to pro...

Applications: Tip provides half the two-wire con- nection to the telephone network, RJ-11 Pin 3. A 1500 volt barrier isolates Tip from all other circuits. This isolation must be preserved throughout the system. The battery voltage on Tip may be positive or negative with respect to Ring.

Features: The OPA2228UA/2K5E4 VGA image sensor produces raw VGA digital video data at up to 30 frames per sec- ond. The image data is digitized using an internal 10-bit column ADC. The resulting 10-bit output data includes embedded codes for synchroniza- tion. The data is formatted and transmitte...

· OCM217

· OMTI20506C

Description: Connect the converter per Table 1 for the appropriate input voltage range. Any offset/gain calibration procedures should not be implemented until the device is fully warmed up. To avoid interaction, adjust offset before gain. The ranges of adjustment for the circuits in Figure 2 are guara...

Applications: The OMTI20506C is a high-speed TTL-compatible FET multiplexer/demultiplexer with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The OMTI20506C...

Features: The OMTI20506C is a 2Mbit (256K x 8 bit) Serial Paged Flash Memory accessed by a high speed SPI-compatible bus. The memory can be written or programmed 1 to 256 bytes at a time, using the Page Write or Page Program instruction. The Page Write instruction consists of an integrated Page...

· OP249GH

Vendor:AD   Package Cooled:02+   D/C:1280   

· OHS3227PHYNIXSOP-20

· OP-07CN.DN

Description: Analog video input for R/Pr 1 Analog video input for R/Pr 2 Analog video input for R/Pr 3 Analog video input for G/Y 1 Analog video input for G/Y 2 Analog video input for G/Y 3 Analog video input for G/Y 4 Analog video input for B/Pb 1 Analog video input for B/Pb 2 Analog video ...

Applications: Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implie...

Features: The LT®1568 is an easy-to-use, active-RC filter building block with rail-to-rail inputs and outputs. The internal ca- pacitors of the IC and the GBW product of the internal low noise op amps are trimmed such that consistent and repeat- able filter responses can be achieved. With a single r...

· OF70HA100D2

· OPA4228PA

Description: The serial audio port consists of a shift clock (SCLK pin), a left/right frame synchronization clock (LRCLK pin), and a data input (SDIN pin). The serial audio port supports standard serial PCM formats (Fs = 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, or 192 kHz) stereo. See the ...

Applications: Transmit Input (Differential Inputs) A pair of internally biased line receivers consisting of a squelch detect receiver with offset and noise filtering and a data receiver with zero offset for data signal pro- cessing. Signals meeting squelch requirements are waveshaped and output ...

Features: TWO DAC TWO-CHANNEL OOPA4228PAERATION In phase, two-channel output can be obtained by using two OPA4228PAs and choosing the single DAC mode (setting SDM SEL high). With the use of a high or low input level on LRDAC (OPA4228PA left/right DAC select), each DAC can have its right channel out...

· OP05SJ

· OV07725-VL1A

· OTBX1P

· OPA237NA/3KE4

Vendor:TI   Package Cooled:SOT23-5   D/C:0831+   

Description: READ: The OPA237NA/3KE4 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in a high impedance state whenever CE or OE is high. This dual line control g...

Applications: The OPA237NA/3KE4 has 8-bit binary down counter and D-type Flip Flop. The counter can set up to max 256 counts and synchronous preset (SPE) input can preset the data. When the count value is 0, the next clock pulse presets the data to invert the output. D-type Flip Flop takes the counter outp...

Features: The circuit shown in Figure 1 is used to balance out the offset voltage of inverting amplifiers having a source resis- tance of 10 kΩ or less. A small current is injected into the summing node of the amplifier through R1. Since R1 is 2000 times as large as the source resistance the ...

· OJ-580331-701

Vendor:aleph   Package Cooled:N/A   D/C:05+   

· OP413AY/883

Vendor:ADI/PMI   Package Cooled:888   D/C:CDIP14   

Description: This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT sh...

Applications: High-Bandwidth Data Path (up to 500 MHz (1)) 5-V Tolerant I/Os With Device Powered Up or Powered Down Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 5 Ω Typ) Rail-to-Rail Switching on Data I/O Ports C 0- to 5-V Switching With 3.3-V VCC C 0- to 3.3-...

Features: sGENERAL DESCRIPTION The OP413AY/883 is a color TFT signal processor for NTSC.It contains Y/C separator circuit, color signal modulator, count down circuit , RGB demodulator , RGB interface , side black control circuit, PWM control circuit and common pole driver, required by color TFT ...

· OP207EZ/AZ

· OP494GSOP494GSOP494GS

· OPA675KG

Description: • Fully static operation and Tri-state output • TTL compatible inputs and outputs • Battery backup(L/LL-part) -. 2.0V(min) data retention • Standard pin configuration -. 32 - SOP - 525mil -. 32 - TSOPI - 8X20(Standard)

Applications: • SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC 3.3V Power Supply User Selectable 3.3V/2.5V I/O 12000 PLD Gates / 256 Macrocells Up to 192 I/O Pins 256 Registers High-Speed Global Interconnect SuperWIDE 32 Generic Logic Block (GLB) Size for Optimum Performanc...

Features: The PCM58P accepts TTL-compatible logic input levels. Noise immunity is enhanced by the use of Schmitt trigger input architectures on all input signal lines. The data format of the PCM58P is binary twos complement (BTC) with the most significant bit (MSB) being first in the serial input b...

· OP15AJ/883C

Description: Parameter SENSOR INPUT Measurement Range1 Nonlinearity Package Alignment Error Alignment Error Cross Axis Sensitivity SENSITIVITY (Ratiometric)2 Sensitivity at XOUT, YOUT Sensitivity Change due to Temperature3 ZERO g BIAS LEVEL (Ratiometric) 0 g Voltage at XOUT, YOUT Initial ...

Applications: • LDO with Integrated Microcontroller Reset Monitor Functionality • Low Input Supply Current (80 µA, typical) • Very Low Dropout Voltage • 10 µsec (typ.) Wake-Up Time from SHDN • 300 mA Output Current • Standard or Custom Output and Detected ...

Features: The OP15AJ/883C is compatible with FSK and FSK plus CAS (CPE Alerting Signal) based Caller ID services around the world. Caller ID is the generic name for a group of services offered by telephone operating companies whereby information about the calling party is delivered to the subscriber. I...

· OMB5612R-V1.1

· OP37GS-REEL7

Applications: The ISSI IS62LV12816LL is a high-speed, 2,097,152-bit static RAM organized as 131,072 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power co...

Features: Reading the OP37GS-REEL7 via the SO (Serial Output) pin requires the following sequence. After the CS line is pulled low to select a device, the READ instruction is transmitted via the SI line followed by the byte ad- dress to read. Upon completion, any data on the SI line will be ignored. Th...

· OP42CZ

Description: If the cell voltage exceeds the overvoltage threshold for 1 second, charging is disabled; however, discharge current is still allowed. This feature of the IC is explained further in the controlled charge/discharge mode section of this document.

Applications: If you have any marketing or sales questions, please contact: Lawrence Liu, at ITE Taiwan: E-mail: lawrence.liu@ite.com.tw, Tel: 886-2-2912-6889 X6071, Fax: 886-2-26578561 David Lin, at ITE U.S.A: E-mail: david.lin@iteusa.com, Tel: (408) 530-8860 X238, Fax: (408) 530-8861 Don Ga...

Features: Notes: 8. This parameter is the delay from an input signal applied to a dedicated input pin to a combinatorial output on any output pin. This delay assumes no expander terms are used to form the logic function. 9. This parameter is the delay associated with an input signal applied to an I/...

· OV511PLUS

Vendor:omnivision   Package Cooled:SMD   D/C:03+   

Description: The 20 outputs from the GLB can drive both the Big Fast Megablock Routing Pool within the Big Fast Megablock and the Global Routing Plane between the Big Fast Megablocks. The Big Fast Megablock Routing Pool con- tains general purpose tracks which interconnect the six

Applications: Additionally, the ASLIC device and ASLAC device have integrated self test and line test capabilities to resolve faults to the line or line circuit. The integrated test capability is crucial for remote applications where dedicated test hardware is not cost effective. The Technical Refere...

Features: The OV511PLUS uses the familiar AND/OR logic array structure, which allows direct implementation of sum-of-products equations. This device has a programma- ble AND array which drives a fixed OR array. The OR sum of products feeds an "Output Macro Cell" (OMC), which can be indiv...

· ON4832(BFG540X)

Vendor:PHILIPS   Package Cooled:SOT-143   D/C:05+   

Description: • Low VCE (on) Non Punch Through IGBT Technology. • Low Diode VF. • 10µs Short Circuit Capability. • Square RBSOA. • Ultrasoft Diode Reverse Recovery Characteristics. • Positive VCE (on) Temperature Coefficient. • Super-247 Package.

Applications: The ON4832(BFG540X) front view options (ON4832(BFG540X)-007/-037) and a top view packaging option (ON4832(BFG540X)-008/-038) come with integrated shield that helps to ensure low EMI emission and high immunity to EMI field, thus enhancing reliable performance.

Features: The ON4832(BFG540X)/ON4832(BFG540X) also feature one adjustable input with a nominal threshold level at 0.5V, another input with three possible input threshold levels, and three supply tolerances for possible margining. These features provide versatility for any kind of system requiring dual s...

· OP290E2

Vendor:IC   Package Cooled:DIP   D/C:0248+   

· OM7439N

· OPA4650AU

· OP04GH

Vendor:AD   Package Cooled:02+   D/C:1280   

· OPA404AP

· OP07GPZ

· OM5232FBP507

Description: The bq24007 and bq24008 provide the timer-enable function, allowing the host to disable the charge timer when charge current is shared with a load or when the battery is absent. This feature is ideal for applications such as cellular phones, PDAs, and internet appliances.

Applications: The OM5232FBP507 is a high performance, low cost USB2.0 CompactFlash-single card reader controller. With the integration of GenesysLogic own design USB 2.0 high speed UTMI transceiver, the OM5232FBP507 has made a conspicuous improvement with full speed USB 1.1 card readers on data transfer r...

Features: The OM5232FBP507/OM5232FBP507/OM5232FBP507 are bridged audio power amplifiers intended for devices with internal speakers and headsets. The OM5232FBP507/OM5232FBP507/ OM5232FBP507 are capable of delivering 330mW of continu- ous power into a 32Ω load, or 200mW into a 16Ω load with ...

· OM5232FBP-507

Vendor:PHI   Package Cooled:97+   D/C:DIP   

Description: • Four-channel, 8-bit A/D converter • 8-bit real time clock/counter (TMR0) with 8-bit programmable prescaler • Interrupt on pin change (GP0, GP1, GP3) • 1,000,000 erase/write cycle EEPROM data memory • EEPROM data retention > 40 years

Applications: Single 5 V 10% Power Supply Fully Static No Clock or Timing Strobes Necessary Fast Access Times: 12/15/20/25 ns Equal Address and Chip Enable Access Times Output Enable (G) Feature for Increased System Flexibility and to Eliminate Bus Contention Problems • Low Power Operation:...

Features: The OM5232FBP-507 uses a novel architecture where the external loop antenna is tuned to the internal UHF synthesizer. This transmitter is designed to comply worldwide UHF unlicensed band intentional radiator regulations. The IC is compatible with virtually all ASK/OOK (Amplitude Shift Key...

· OIZI867908A

Vendor:ZILOG   Package Cooled:SMD   D/C:07+   

Description: • CASE: Hermetically sealed DO-213AB glass MELF package • TERMINALS: End caps, tin-lead plated solderable per MIL-STD-750, method 2026 • POLARITY: Cathode indicated by band. • MARKING: Cathode band only • TAPE & REEL optional: Standard per EIA-481-B ...

Applications: A programmable digital audio effects processor enables bass, treble, midrange, or equalization playback processing. The digital audio data format is programmable to work with popular audio standard protocols (I2S, DSP, Left/Right Justified) in master or slave mode, and also includes an ...

Features: TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utili...

· OP32JSG

· ORBIT61505A

Vendor:N/A   Package Cooled:PQFP-80   D/C:01   

Description: Caveat: This calculation has assumed that the voltage drops due to the various components (such as the resistive drop of the MOSFETs and inductor or current sense resistor, or the forward voltage of a schottky in a non-synchronous con- verter) are negligible compared to the input and outp...

Applications: 1394b-2002 at S100, S100B, S200, S200B, S400, and S400B Signaling Rates (B Signifies 1394b Signaling) Fully Supports Provisions of IEEE 1394a-2000 and 1394-1995 Standards for High Performance Serial Bus Fully Interoperable With Firewire, SB1394, DishWire, and i.LINK&...

Features: Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (JA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax W...

· OP10FY

Vendor:AD   Package Cooled:N/A   D/C:99+/00+   

Description: Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku...

Features: The OP10FYSB is a head amplifier IC supporting the digital servo. Combination of this IC and the MN662710RA (digital servo processor + signal processing + DAC/DF) allows the rational CD ROM system to be constructed with small number of external parts.

· OPA350EA/250

Description: Notes: 1. Load and Line Regulation are specified at a constant junction temperature. Pulse testing with low duty cycle is used. Changes in output voltage due to heating effects must be taken into account separately. 2. Short Circuit protection is only assured up to VIN = 35V. 3. If not t...

Applications: The HDB3 Encoder is responsible for converting the incoming NRZ data into pseudo-ternary form for transmis- sion over a PCM link. This conversion is carried out in accordance with the HDB3 coding laws specified in CCITT Recommendation G. 703 The data to be encoded is input on the NRZ D...

Features: The OPA350EA/250 is a new generation ADSL chipset from STMicroelectronics. It is highly integrated and has the flexibility to offer all standards, all an- nexes while being fully optimised for CPE applica- tions. It provides all the required functions to implement a complete Utopia rate...

· OP27AJ8/883

Description: The LTC®3704 is a wide input range, current mode, positive-to-negative DC/DC controller that drives an N-channel power MOSFET and requires very few external components. Intended for low to high power applications, it eliminates the need for a current sense resistor by utilizing the power ...

Applications: An outstanding feature of the OP27AJ8/883 is its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with a 8-word line length.

Features: • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ...

· OP90GP

Description: FEATURES HIGH SURGE CAPABILITY TRANSIL ARRAY IPP = 40 A (8/20µs) PEAK PULSE POWER : 300 W (8/20µs) UP TO 6 UNIDIRECTIONAL TRANSIL FUNC- TIONS LOW CLAMPING FACTOR (VCL / VBR) AT HIGH CURRENT LEVEL LOW LEAKAGE CURRENT ESD PROTECTION UP TO 15kV

Applications: First-In/First-Out dual-port memory 256 x 9 organization (IDT7200) 512 x 9 organization (IDT7201) 1K x 9 organization (IDT7202) Low power consumption Active: 770mW (max.) Power-down: 2.75mW (max.) Ultra high speed12ns access time Asynchronous and simultaneous read and write Full...

Features: The Atmel OP90GP Smart Internet Appliance Processor (SIAP™) is a high-perfor- mance processor specially designed for Internet appliance applications, such as Internet telephony (Voice-over-Internet Protocol C VoIP). The OP90GP is a derivative version of the AT75C310. The device is bui...

· OP77AD/883

Vendor:OP   Package Cooled:06+   D/C:500   

· OLS130URSYGXDT

Vendor:osa   Package Cooled:osa   D/C:dc99   

Description: Agilent Technologies offers a wide variety of codewheels for use with Agilents HEDS-9000, HEDS-9100, HEDS-9040, and HEDS-9140 series Encoder Modules. Designed for many environments, applications, and budgets, Agilent codewheels are available in Glass, Film, and Metal. These code...

Applications: cycle, allowing one continuous read operation without the need of additional address sequences. To perform a continuous read, an opcode of 68H or E8H must be clocked into the device followed by 24 address bits and 32 dont care bits. The first two bits of the 24-bit address sequence are rese...

Features: The 80C186XL contains logic which provides programmable chip-select generation for both mem- ories and peripherals In addition it can be programmed to provide READY (or WAIT state) gen- eration It can also provide latched address bits A1 and A2 The chip-select lines are active for all me...

· OPA4343UA/2K5

Description: Three Input Comparators with Schmitt-trigger Characteristic Input Clamping Current Capability of 10 mA Integrated Protection Cells (EMC, ESD, RF) Dedicated to all Input Stages Common Shutdown by Junction-temperature Monitor Reset with Hysteresis at Low Voltage ESD Protection Acording...

Applications: 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.

· OP492GBCOP492GBCOP492GBC

· OHS3130U

Vendor:Optek   Package Cooled:n/a   D/C:08+   

· OKI58371

· ORT4622BG432M

Vendor:ORCA   Package Cooled:BGA   D/C:10   

· OPA121KM-BI

· OP42GP0OP42GP0OP42GP0

· OEC3036B

Vendor:OEC   Package Cooled:N/A   D/C:9+   

· OR2T40B8PS208-DB

Description: The on-board Flash program memory is accessible through the ISP serial interface. Holding RST active forces the device into a serial programming interface and allows the program mem- ory to be written to or read from, unless one or more lock bits have been activated.

Applications: Port 3: Port 3 is an 8-bit I/O port with a user configurable output type. Port 3 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. the operation of port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is...

Features: The Hyundai OR2T40B8PS208-DB Series are Dual In-line Memory Modules suitable for easy interchange and addition of 256Mbytes memory. The Hyundai OR2T40B8PS208-DB Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with t...

· OCETGLJTNF-80MHZ

· OP420BY883COP420BY883COP420BY883C

· OP05HJ

Description: Hynix HYMD216726A(L)6J-J series is designed for high speed of up to 166MHz and offers fully synchronous opera- tions referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes...

Applications: This high speed Digital multiplexer utilizes advanced silicon- gate CMOS technology Along with the high noise immunity and low power dissipation of standard CMOS integrated cir- cuits it possesses the ability to drive 10 LS-TTL loads The OP05HJ OP05HJ selects one of the 8 data sources de...

Features: The serial Command mode allows access to the OP05HJ control and status registers via a serial control port. In this mode the AD0, AD1, and AD2 lines provide register addresses for data passed through the AD7 (DATA) pin under control of the RD and WR lines. A read operation is initiated when t...

· OP90GC/D

· OP16AMJ8/883B

· OPA37EJ-BSS4

· OPA549F

· OM5178H/HL

Description: The following discussion refers to the schematic in figure 2 below. A FET current source is used to bias a 6.3V zener diode. The zener voltage is divided by the resistor network R1 and R2. This voltage is then applied to the noninverting input of the operational amplifier which amplifies th...

Applications: Shutdown Mode Shutdown mode is enabled by setting the shutdown bit in the Configuration register via the SMBus. Shut- down mode reduces power supply current to 1 µA typical. In interrupt mode O.S. is reset if previously set and is undefined in Compatator mode during shutdown. The SMBus...

Features: This method fails if a user applies RESET during the FPGA configuration process. The FPGA aborts the configuration and then restarts a new configuration, as intended, but the PROM does not reset its address counter, since it never saw a High level on its OE input. The new configuration, ...

· OP200-014

· OEC7098A

Vendor:ORION   Package Cooled:QFP   D/C:2003   

Description: DESCRIPTION This MOSFET series realized with STMicroelec- tronics unique STripFET™ process has specifical- ly been designed to minimize input capacitance and gate charge. It is therefore suitable as primary switch in advanced high-efficiency, high-frequency isolated DC-DC convert...

Features: The dual charge pump in the OEC7098A is capable of delivering 600mA peak output current. Two cur- rent-controlled paths are available for users of dual flash LEDs that prefer current matching. Each LED channel can be easily programmed in 32 steps with a single GPIO output through the AS2Cwire...

· OP47/GSOP47/GSOP47GS

· OARS1R025FLF

Description: M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port Separate upper-byte and lower-byte contr...

Applications: Input HIGH Voltage (Input pins) Input HIGH Voltage (I/O pins) Input LOW Voltage (Input and I/O pins) Input HIGH Current (Input pins) Input HIGH Current (I/O pins) Input LOW Current (Input pins) Input LOW Current (I/O pins) High Impedance Output Current (3-State Output pins) Clamp Diode V...

Features: The modem operates at 14400, 12000, 9600, 7200, 4800, 2400, or 300 bps. The modem supports the V.17 signaling rates of 14400, 12000, 9600, and 7200 bps using trellis-coded modulation (TCM). In addition, the modem supports V.27 ter and V.17 short trains.

· OPV320

· OP193FS-REEL

Description: As is the case with the A-Series DC tachometer generator, the B-Series also comes in instrument and industrial configurations. Depending on the unit, the output voltage ranges between 11 and 24 V/1000 RPM. Electrical characteristics, ripple, linearity and temperature effects are the sam...

Applications: The functions of the device include analog input multiplexing, on-chip track and hold function, 8-bit analog-to-digital conversion and an 8-bit digital-to-analog conversion. The maximum conversion rate is given by the maximum speed of the I2C-bus.

Features: The OP193FS-REEL PCI interface has the following features: I 33-MHz and 66-MHz 64-bit intelligent bus master conventional PCI interface (PCI 2.2) I 64-bit host memory addressing (dual-address cycle) I Five-channel DMA controller I 32-bit PCI target mode for communication with the host ...

· OTI033AD

Description: MBM29DL16XTE/BE are organized into two banks, Bank 1 and Bank 2, which can be considered to be two separate memory arrays as far as certain operations are concerned. These devices are the same as Fujitsus standard 3 V only Flash memories with the additional capability of allowing a normal n...

Applications: The Philips 28L198 Octal UART is a single chip CMOSCLSI communications device that provides 8 full-duplex asynchronous channels with significantly deeper 16 byte FIFOs, Automatic inCband flow control using Xon/Xoff characters defined by the user and address recognition in the wake up mode...

Features: When connected to a 1394a-2000 compliant node, the OTI033AD provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The PHY contains three independent TPBIAS circuits (one for each port). This bias voltage, when seen through a cable by a remote receiver, indicate...

· OP42NBCGDIE4OP42NBCGDIE4OP42NBCGDIE4

· OM5955ET/C2(RF21010)

Vendor:PHILIPS   Package Cooled:5,000   D/C:09+   

· OTI011DBT07

Description: Description The CE pin is used for interfacing with the CPU. Should be held high to allow access to the CPU. Incorporates a pull-down resistor. Should be held low or open when the CPU is powered off. Allows a maximum input voltage of 5.5v regardless of supply voltage. The SCLK pin is used to ...

Applications: followed by the new command code of 8 bits (1st byte of the protocol.) If the OTI011DBT07 is still busy with the nonvolatile write operation, it will issue a no-ACK in response. If the nonvolatile write operation has completed, an ACK will be returned and the host can then proceed with ...

Features: For the most efficientuse of thesetwo control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected...

· OPA2682UA

Vendor:BB/TI   Package Cooled:2828   D/C:SOP8   

· OPA620SD

· OPA134PAG4

Vendor:BB   Package Cooled:DIP-8   D/C:06+   

Description: Setting the LED Current The regulated output current is determined by the selection of the sense Resistor connected from the ISENSE input to ground, and the maximum user defined voltage of the CTRL input. The desired output current, (typically 15mA to 20mA for white LEDs), is derived using ...

Applications: BACKPLANE TEST DATA OUTPUT: This output drives test data from the STA111 and the local TAPs, back toward the scan master controller. This output has 24mA of drive current. When the device is power-off (VDD = 0V or floating), this output appears to be a capacitive load (Note 4).

Features: The triple driver IC includes three non-inverted and current-limited output stages with an open collector. Common thermal shutdown protects the outputs against critical junction temperatures. Each output can sink a current of 20 mA, parallel output opera- tion is possible. The digital input...

· OP27GE

Description: C 15 mA Active Current C 20 µA CMOS Standby Current Fast Read Access Time - 200 ns Automatic Page Write Operation C Internal Address and Data Latches for 64 Bytes C Internal Control Timer Fast Write Cycle Times C Page Write Cycle Time: 10 ms Maximum C 1 to 64 Byte Page Write ...

Applications: Sync separation Pin 7 threshold voltage VTH7H, VTH7L Impress external DC voltage on TP9 and raise gradually from 0V. TP9 level when TP11 level goes from high to low is VTH7H. Lower gradually from 5V. TP9 level when TP11 level goes from low to high is VTH7L.

Features: This product contains beryllium oxide. The product is entirely safe provided that the BeO discs are not damaged. All persons who handle, use or dispose of this product should be aware of its nature and of the necessary safety precautions. After use, dispose of as chemical or special waste a...

· OP07AJ/883/MILADOP07AJ/883/MILADOP07AJ883MILAD

· ORT82G5-1BM680C

Description: Fully static operation and Tri-state outputs TTL compatible inputs and outputs Low power consumption Battery backup(LL-part) -. 2.0V(min) data retention • Standard pin configuration -. 32pin 525mil SOP -. 32pin 400mil TSOP-II (Standard and Reversed)

Applications: Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied...

Features: Mechanical Characteristics: • Case: Epoxy, Molded • Weight: 217 mg (approximately) • Finish: All External Surfaces Corrosion Resistant and Terminal Leads are Readily Solderable • Lead and Mounting Surface Temperature for Soldering Purposes: 260C Max. for 10 Seconds &...

· OP06

Description: +3 Volt single power supply Low power CMOS design 4-Wire serial interface 2.5V data output voltage swing AUX input with analog clamp and programmable gain Four color gain and offset registers Digital black level clamp Small 48-lead LQFP package Supports interlace and progressive scan CCDs.

Applications: • Extended Data-Out (EDO) Page Mode access cycle • TTL compatible inputs and outputs • Refresh Interval: -- 2,048 cycles/32 ms -- 4,096 cycles/64 ms • Refresh Mode: RAS-Only, CAS-before-RAS (CBR), and Hidden • JEDEC standard pinout • Single p...

Features: Input a signal to the Pin18 and measure the output between the Pins22 and 23 at an output distortion factor of 5%. Input a signal (C45dBm) to the Pin18 and mea- sure an output change between the Pins22 and 23 when IL changes from 80mA to 30mA. Input a signal (C45dBm) to the Pin18 and ...

· OP83902V

· OP32CJ

· OP07-198J

· OP279GS-REEL7

Vendor:adi   Package Cooled:S&D   D/C:08+   

Description: AC LINE SWITCH BASIC APPLICATION The ACS120 device is well adapted to Washing machine, dishwasher, tumble drier, refrigerator, air-conditioning systems, and cookware. It has been designed especially to switch on & off low power loads such as solenoid, valve, relay, dispenser, micro-moto...

Applications: Single Chip With Easy Interface Between UART and Serial-Port Connector of IBM™ PC/AT ™ and Compatibles Meets or Exceeds the Requirements of ANSI Standard TIA/EIA-232-F and ITU Recommendation V.28 Designed to Support Data Rates up to 120 kbit/s Pinout Compatible With SN75C185 and...

Features: The OP279GS-REEL7 is a monolithic CMOS integrated circuit that includes stereo digital-to-analog converters and support circuitry in a small 28-lead SSOP package. The data converters use TIs advanced-segment DAC architecture to achieve excellent dynamic performance and improved tolerance...

· OA2237UA

Description: Figure 1 shows a typical application circuit. The regulator is enabled any time the shutdown input is at or above VIH. And shutdown (disabled) when SHDN is at or below VIL. SHDN maybe controlled by a CMOS logic gate, or I/O port of a micro controller. If the SHDN input is not. Required,...

Applications: Intended for analog and digital satellite receivers, the low noise block converter regulator (LNBR) is a monolithic linear and switching voltage regulator, specifically designed to provide the power and the interface signals to the LNB downconverter via the coaxial cable.

Features: The topping charge is applied for a minimum of two (2) hours. The current consists of the same pulse technique used during the fast charge stage; however, the delay time is extended as shown in Figure 5. Extending the delay time between charge pulses allows the same charging current used as...

· OM5932ATT/C3

Vendor:NXP   Package Cooled:TSSOP32   D/C:0705+   

Description: ** Required for stability. Must be rated for 10 µF minimum over intended operating temperature range. Effective series resistance (ESR) is critical, see curve. Locate capacitor as close as possible to the regulator output and ground pins. Capacitance may be increased without bound.

Applications: whichever occurs first. During the Erase operation, the only valid reads are Toggle Bit and Data# Polling. See Table 3 for the command sequence, Figure 6 for timing diagram, and Figure 17 for the flowchart. Any commands issued during the Chip-Erase operation are ignored.

Features: Functionally Equivalent to AMDs AM29821 Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance State Buffered Control Inputs to Reduce dc Loading Effects Package Options Include Plastic Sma...

· OP482G

Description: Operating Voltage Range of 1.15 V to 5.5 V Output Current Capability in Excess of 50 mA Low Current Consumption of 122 mA Power Saving Shutdown Input for a Reduced Current of 0.4 mA Operation at 35 kHz Low Output Resistance of 26 W Space Saving TSOP−6 Package Pb−Free Package...

Applications: FEATURES Selectable 2-, 3-, or 4-Phase Operation at up to 1 MHz per Phase 14.5 mV Worst-Case Differential Sensing Error over Temperature Logic-Level PWM Outputs for Interface to External High Power Drivers Active Current Balancing between All Output Phases Built-In Power Good/Crowb...

Features: Maximum rated frequency: 133 MHz Low cycle-to-cycle jitter Input to output delay, less than 200ps Internal feedback allows outputs to be synchronized to the clock input • Operates at 3.3V VDD • Space-saving Packages: 150-mil SOIC (W) 173-mil TSSOP (L)

· OP482G-

Description: The following discussion refers to the schematic in figure 2 below. A FET current source is used to bias a 6.3V zener diode. The zener voltage is divided by the resistor network R1 and R2. This voltage is then applied to the noninverting input of the operational amplifier which amplifies th...

Applications: (1) All typical values are at TA = +25C. (2) Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range of the transfer curve for VIN+ = −250mV to +250mV, expressed either as the number of LSBs or as a percent of measured ...

Features: The Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010 for the OP482G- (see Fig. 5). The next three significant bits (A2...

· OPA705NA/250

Description: - Updated SPI electrical characteristics. - Updated Derivative Differences table. - Added ordering number example. - Added Detailed Register Map. - Changed Internal Pull Resistor column of signal table. - Added pull device description for MODC pin. - Corrected XCLKS figure title...

Applications: Hynix HYMD216726A(L)6J-J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 16Mx72 high-speed memory arrays. Hynix HYMD216726A(L)6J-J series consists of eighteen 16Mx16 DDR SDRAM in 400mil TSOP II packages on a 184pin glas...

Features: C Two 64-voice RISC DSP Cores C Two High-speed CISC Control Processors C Versatile Programmable Digital Audio Routing Between the Two DSPs Voices Can Be Allocated for Synthesis and/or Effects and/or Audio Processing Maximum Single-shot PCM Wavesize of 4M Samples (93 Seconds @ 44.1 kHz) S...

· OPA358U

Description: Notes: 1. The algebraic convention, where the most negative value is a minimum and the most positive is a maximum, is used in this data sheet. 2. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing. 3. Guaranteed by design 4. ∆RON = ∆RON ma...

Applications: The Hitachi HM5264165F is a 64-Mbit SDRAM organized as 1048576-word 16-bit 4 bank. The Hitachi HM5264805F is a 64-Mbit SDRAM organized as 2097152-word 8-bit 4 bank. The Hitachi HM5264405F is a 64-Mbit SDRAM organized as 4194304-word 4-bit 4 bank. All inputs and outputs are referred to ...

Features: The OPA358U-1 and OPA358U-2 are dual high-side switches with active-high and active-low enable inputs, respec- tively. Fault conditions turn off or inhibit turn-on one or both of the output transistors, depending upon the type of fault, and activate the open-drain error flag transistors to pu...

· OC1072

· OPA4241UA/2K5G4

Vendor:TI   Package Cooled:SOP14   D/C:06+   

Description: Performance Latest processor technology, Intel® Pentium® 4 Processor with HT Technology 3.40 GHz Max. 4.0 GB DDR-SDRAM for memory demanding applications AGP 8x Pro 50 to deliver enough energy to accommodate even the most powerful graphics subsystems Optional SCSI control...

Applications: This data sheet has been carefully CORPORATION • 5980 NORTH SHANNON ROADassumed for possible inaccuracies • USA • APPLICATIONS HOTLINE: 1 (800) 546-2739APEX MICROTECHNOLOGY checked and is believed to be reliable, however, no responsibility•is TUCSON, ARIZONA 85741 or ...

Features: • Industrial applications for daisy chaining multiple devices • Industrial control in latency critical applications • Port redundancy and port monitoring • Security cameras • VoIP phone and ATA adaptors

· OM5951BHL/C203

Vendor:PHILIPS   Package Cooled:QFP64   D/C:O1   

Description: © 2000 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE...

Applications: The Loop Filter is a low pass filter. This low pass filter ensures that the network jitter requirements are met for an input reference frequency of 19.44 MHz. The corner frequency of the Loop Filter is configurable with an external capacitor and resistor connected to the LPF pin and ground as ...

Features: See Figure 2. Temperature range for Y version is −40C to +125C. Guaranteed by design and characterization, not subject to production test. All input signals are specified with tr = tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Digital output timing measur...

· OZ-SS-124L

Vendor:OEG   Package Cooled:relay   D/C:08+   

Description: The signal conditioner demodulates the amplifier output signal and converts it to a binary signal. It compares the carrier signal with the 50% reference level (see Ref1 in Figure 5) and delivers a logical 1, if the carrier signal stays below the reference and a logical 0, if it exceeds the...

Applications: ICCSupply currentVCC = MAX,All outputs disabled5270mA † All typical values are at VCC = 5 V, TA = 25C, and VIC = 0. ‡ The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for threshold levels only. No...

Features: Note 1: The OZ-SS-124L are guaranteed to meet performance specifications from 0C to 85C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls.

· OPA6044

Vendor:BB   Package Cooled:SOP-8   D/C:04+   

· OP117AZ

· ODM00003524-100

Features: The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the users own r...

· OPA356SM/883B

· OP376GS

Vendor:N/A   Package Cooled:N/A   D/C:09+   

· OPA777UA

Vendor:BB/TI   Package Cooled:SOP8   D/C:04+   

Description: The IDTQS74FCT2245T is an 8-bit non-inverting transceiver that has three-state outputs, ideal for bus-oriented applications. The Transmit/ Receive (T/R) input determines the direction of data flow, either from A to B or B to A, and the Output Enable (OE) input enables the selected port for...

Applications: After power-on-reset, the ATA5275 is in standby mode. For minimum power consumption, only the internal 5 V supply and the DIO line interface are active. The IC can be activated by the external control unit via the serial interface. The DIO line is called logic high if it is pulled up to the...

Features: CT - This is the oscillator timing pin. The free-running frequency can be set by connecting a timing capacitor to this pin. The oscillator produces a sawtooth waveform with a programmable frequency range of 100kHz to 1.2MHz. Figure 4 may be used as a guideline in selecting the capacitor valu...

· OM5959HL

Vendor:PHILIPS   Package Cooled:QFP-48   D/C:07+   

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